應用於IEEE 802.3bp車用乙太網路之硬決定與軟決定里德所羅門解碼器架構與電路設計;Architecture and circuit Design of Hard-Decision/Soft-Decision Reed-Solomon Decoding for IEEE 802.3bp Automotive Ethernet

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Title:	應用於IEEE 802.3bp車用乙太網路之硬決定與軟決定里德所羅門解碼器架構與電路設計;Architecture and circuit Design of Hard-Decision/Soft-Decision Reed-Solomon Decoding for IEEE 802.3bp Automotive Ethernet
Authors:	吳宗桓;Wu, Zong-Huan
Contributors:	電機工程學系
Keywords:	里德所羅門碼;軟決定解碼;錯誤更正碼;Reed-Solomon Codes;Soft-Decision Decoding;Error Correction Code
Date:	2021-10-27
Issue Date:	2021-12-07 13:26:24 (UTC+8)
Publisher:	國立中央大學
Abstract:	本論文依據IEEE Std 802.3bpTM-2016標準的車用乙太網路規格，RS(450, 406)解碼器是專用於此通訊系統，由於經過高速傳輸，解碼器的選擇就相當重要，且解碼過程最為繁複，需先找出錯誤位置與對應之錯誤值再加以更正。在計算完徵狀值後，採用低複雜度的Berlekamp-Massey演算法、Chien search演算法和Forney演算法來硬性解碼。為了能更進一步提升更正效能，在相同碼率下軟性解碼能提高錯誤更正能力，依據經過通道後所接收的軟性資訊，計算出每個位元的可信度，並將Chase演算法加入到硬決定解碼中達到軟決定解碼，一般的Chase演算法是需要多組硬決定解碼器來計算出多組候選碼並從中選出一最佳解，不過本論文在Chase演算法增加一個判斷的決定器後，只需要一組硬決定解碼器就能完成軟決定解碼。硬體電路架構使用Verilog硬體描述語言來設計，並透過Design Compiler與 IC Compiler來驗證在製程為TSMC-40nm下的電路功能。;This thesis is based on the IEEE Std 802.3bpTM-2016 specification for automotive Ethernet, an RS(450, 406) decoder is specified in this transmission. Due to high-speed transmission, the choice of decoder is very important, and the decoding process is the most complicated. The error location and the corresponding numeric error should be found before correction. After syndrome computation, the low-complexity Berlekamp-Massey Algorithm, Chien search Algorithm, and Forney Algorithm are used for hard decoding. In order to further improve the correction performance, the soft decoding can improve the ability of error correction at same code rate. Based on the received soft information, the reliability of each symbol is calculated, and the hard decoding is enhanced by using the Chase algorithm to achieve soft decoding. The general Chase algorithm requires multiple hard decoders to calculate multiple candidate code. In this thesis, after adding a decision making unit to Chase algorithm, only a set of hard decoders are needed to complete the soft decoding. This design is coded on Verilog HDL, and the circuit functionality is verified by Design Compiler and IC Compiler at TSMC-40nm process.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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