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    Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/88376


    Title: 應用於第五代通訊之B類連續模式氮化鎵功率放大器暨互補式金氧半導體堆疊式功率放大器之研製;Implementations on Class-B Continuous Mode GaN Power Amplifiers and CMOS Stacked Power Amplifier for 5G Communications.
    Authors: 羅時凱;Lo, Shih-Kai
    Contributors: 電機工程學系
    Keywords: 功率放大器;連續B類模式;氮化鎵;堆疊式架構;第五代行動通訊技術;power amplifier;continuous B mode;Gallium nitride;stacked FET;5th generation mobile networks
    Date: 2022-04-21
    Issue Date: 2022-07-14 01:04:13 (UTC+8)
    Publisher: 國立中央大學
    Abstract: 本論文使用穩懋半導體公司(WINTM)所提供之 0.25-µm GaN/SiC 製程與台灣積體電路製造股份有限公司(tsmcTM ) 所提供之 0.18-µm CMOS 1P6M 製程,分別進行 n77 頻段之氮化鎵連續 B 類模式功率放大器、n77-n79 頻段之氮化鎵連續 B 類功率放大器以及n77-n79 頻段之互補式金氧半導體堆疊式功率放大器之設計。
    第一顆提出應用於 n77 頻段之氮化鎵連續 B 類模式功率放大器,輸出匹配電路採用連續 B 類模式,針對基頻和二階諧波阻抗進行匹配,達成寬頻高效率的特性,並且透過閘級偏壓的挑選,改善軟性增益壓縮,進而使得有良好的 AM-AM 的特性。量測結果顯示最佳傳輸增益為 20.7 dB,操作頻寬為 3.3-4.2 GHz,飽和輸出功率為 39.3 dBm,功率附加效率最高可達 51 %,晶片面積為 4.75 (2.73 × 1.74) mm2。
    第二顆提出應用於 n77- n79 頻段之氮化鎵連續 B 類模式功率放大器,透過閘級偏壓的挑選,改善功率放大器非線性的特性,輸出匹配電路使用連續 B 類模式,達成寬頻高效率的操作,輸入匹配網路使用帶通濾波器架構,改善整體電路增益平坦性。量測結果顯示最佳傳輸增益為 20.2 dB,操作頻寬為 3.3-5.0 GHz,飽和輸出功率為 39 dBm,功率附加效率最高可達 45 %,晶片面積為 4.83 (2.76 x 1.75 ) mm2。
    第三顆提出應用於 n77- n79 頻段之互補式金氧半導體功率放大器,透過使用堆疊式架構,改善了汲極端擺幅受到 CMOS 製程本身較低的崩潰電壓和較高的膝部電壓的限制,進而提升整體電路輸出功率,並且透過偏壓的選擇減緩增益壓縮的特性,達成 1dB功率壓縮點和飽和輸出功率的距離約為 1 dB,輸出和輸入匹配皆採用了對稱型磁耦合共振腔,達成寬頻的操作行為。模擬結果顯示最佳傳輸增益為 20.4 dB,操作頻寬為 3.3-5.0 GHz,飽和輸出功率為 27.6~28.3 dBm,功率附加效率最高可達 20~25.2 %,晶片面積為 3.84 (2.4 × 1.6) mm2。

    ;This thesis developed three power amplifiers (PAs) that were designed and fabricated in WINTM 0.25-µm GaN/SiC and tsmcTM 0.18-µm CMOS 1P6M technology. The first design is a continuous class-B mode power amplifier for n77 band (3.3-4.2 GHz) application in GaN/SiC technology, the second one is a continuous class-B mode power amplifier for n77-n79 band (3.3-5.0 GHz) application in GaN/SiC technology and the third one is a stacked power amplifier for n77-n79 band (3.3-5.0 GHz) application in 0.18-µm CMOS technology.
    The first chip presents a continuous class-B mode power amplifier for n77 band in GaN/SiC technology. The high-efficiency and broadband operations achieved by using continuous class-B mode output matching network which is matched for fundamental and second harmonics impedances. The soft gain compression is improved by proper selection of the gate bias voltage and thus to achieve good AM-AM performance. The measurements illustrate as following, the peak power gain is 20.7 dB, the operations bandwidth is from 3.3 to 4.2 GHz, the saturated output power (Psat) is 39.3 dBm, the peak power added efficiency (PAE) is up to 51 %, and the chip area is 4.75 (2.73 × 1.74) mm2.
    The second chip presents the continuous class-B mode power amplifier for n77-n79 band in GaN/SiC technology. The gate bias voltage is properly set to improve the linearity. The highefficiency and broadband operations are achieved by using continuous class-B mode output matching network. The bandpass filter topology is used in input matching network design to obtain the gain flatness. The measurements show as following, the peak power gain is 20.2 dB, the operations bandwidth is from 3.3 to 5.0 GHz, the Psat is 39 dBm, the peak PAE is to 45 %,and the chip area is 4.83 (2.76 × 1.75) mm2.
    The third chip presents the stacked power amplifier for n77-n79 band application in 0.18- µm CMOS technology. The stacked topology is adopted to sustain the large swings at the output drain node from low breakdown voltage and high knee voltage limitations in CMOS technology. Meanwhile, the gate bias voltage is properly set to improve the gain compression performance. The designed PA achieves only 1-dB difference between the output 1-dB power compression
    point (OP1dB) and Psat. The broadband performance is achieved by using symmetrical magnetically coupled resonators at both input and output matching networks. The simulations show as followings, the peak power gain is 20.4 dB, the operations bandwidth is from 3.3 to 5.0 GHz, the Psat is 27.6-28.3 dBm, the peak PAE is to 20~25.2 %, and the chip area is 3.84 (2.4 × 1.6) mm2.
    Appears in Collections:[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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