以CMOS/GaAs/GaN製程實現之應用於n79頻段J類寬頻功率放大器;Implementations on Class-J Wideband Power Amplifiers in CMOS/GaAs/GaN Technologies for n79 Band Applications

NCUIR > College of Electrical Engineering & Computer Science > Graduate Institute of Electrical Engineering > Electronic Thesis & Dissertation > Item 987654321/88400

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/88400

Title:	以CMOS/GaAs/GaN製程實現之應用於n79頻段J類寬頻功率放大器;Implementations on Class-J Wideband Power Amplifiers in CMOS/GaAs/GaN Technologies for n79 Band Applications
Authors:	張瓊文;Chang, Chiung-Wen
Contributors:	電機工程學系
Keywords:	n79頻段;互補式金屬氧化物半導體;砷化鎵;氮化鎵;J類功率放大器;疊接式功率放大器;射頻發射機;記憶效應;鄰近通道功率;誤差向量振福;數位預失真;小型基地站;5G small cell;ACPR;Class-J power amplifier;stacked FET;n79 band;RF transmitter;GaN;GaAs;CMOS;EVM;memory effect;digital pre-distortion
Date:	2022-06-27
Issue Date:	2022-07-14 01:19:57 (UTC+8)
Publisher:	國立中央大學
Abstract:	本論文分別使用tsmc^TM 0.18 μm CMOS、穩懋WINTM 0.15-µm GaAs與0.25-µm GaN三種製程，設計同為操作於n79頻段之J類功率放大器。第二章會先探討n79頻段J類功率放大器，此架構會於之後章節，分別實現在三種不同製程之電路。第三章提出應用tsmc^TM 0.18 μm CMOS製程於n79頻帶之J類功率放大器，電路設計採全積體化之兩層堆疊電晶體結構，量測結果為3-dB頻寬為3.0-5.8 GHz，在n79頻帶內，飽和效率皆大於35%，最大傳輸增益為14.06 dB，飽和輸出功率為20.13 dBm，1-dB 增益壓縮點輸出功率為17.06 dBm，晶片面積為1.2 (1.097 × 1.094) mm2。第四章提出應用WINTM 0.15-µm GaAs製程於n79頻帶之J類功率放大器，電路設計採全積體化之兩級共源極電路架構，量測結果為3-dB頻寬為3.8 – 5.7GHz，在n79頻帶內，飽和效率皆大於35%，最大傳輸增益為25.42 dB，飽和輸出功率為23.43 dBm，1-dB 增益壓縮點輸出功率為22.34 dBm，晶片面積為1.5 (1.5 × 1.0) mm2。第五章提出應用WINTM 0.25-µm GaN製程於n79頻帶之J類功率放大器，電路設計採全積體化之兩級共源極電路架構，量測結果為3-dB頻寬為3.1 – 5.3 GHz，在n79頻帶內，飽和效率皆大於40%，最大傳輸增益為24.56 dB，飽和輸出功率為38.33 dBm，1-dB 增益壓縮點輸出功率為25.16 dBm，晶片有效面積為3.57 (2.223 × 1.606) mm2。第六章為結論，並且比較三種製程各別之優缺點。;The thesis developed three Class J power amplifiers that were designed in tsmc^TM 0.18-µm CMOS, WINTM 0.15-µm GaAs, and WINTM 0.25-μm GaN all for n79-band operations. The second chapter will firstly discuss the n79 band class J power amplifier. This implemented topology in three different process will be addressed in the following chapters. The third chapter proposes a class J power amplifier using tsmc^TM 0.18-μm CMOS process in n79 frequency band. The circuit design adopted a fully integrated two-stacked FET structure. The amplifier achieves a 3-dB bandwidth from 3.0 to 5.8 GHz with small signal gain of 14.06 dB, the peak power added efficiency (PAE) is higher than 35% in n79 band. Continuous Wave (CW) measurements demonstrate a maximum saturated output power of 20.13 dBm and an OP1dB of 17.06 dBm, respectively. The chip size is 1.2 (1.097 × 1.094) mm2. The fourth chapter proposes a class J power amplifier using WINTM 0.15-µm GaAs process in n79 frequency band. The circuit design adopted a fully integrated two-stage common-source circuit structure. The amplifier achieves a 3-dB bandwidth from 3.8 to 5.7 GHz with small signal gain of 25.42 dB, the peak PAE is higher than 35% in n79 band. CW measurements demonstrate a maximum saturated output power of 23.43 dBm and an OP1dB of 22.34 dBm, respectively. The chip size is 1.5 (1.5 × 1.0) mm2. The fifth chapter proposes a class J power amplifier using WINTM 0.25-μm GaN process in n79 frequency band. The circuit design adopts a fully integrated two-stage common-source circuit structure. The amplifier achieves a 3-dB bandwidth from 3.1 to 5.3 GHz with a small signal gain of 24.56 dB, the peak PAE is higher than 40% in n79 band. CW measurements demonstrate a maximum saturated output power of 38.33 dBm and an OP1dB of 25.16 dBm, respectively. The chip effective area is 3.57 (2.223 × 1.606) mm2. The fifth chapter proposes conclusions of the thesis. The advantages and disadvantages of these processes will be analyzed and discussed in the thesis.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

Files in This Item:

File	Description	Size	Format
index.html		0Kb	HTML	137	View/Open

社群 sharing

Loading...