系統晶片類比數位轉換器測試之數位信號處理程式庫; DSP Library for SOC ADC Testing

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Title:	系統晶片類比數位轉換器測試之數位信號處理程式庫;DSP Library for SOC ADC Testing
Authors:	林宜宏;Yi-Horng Lin
Contributors:	電機工程研究所
Keywords:	類比數位轉換器;信號雜訊比;有效位元數;類比數位轉換器動態測試;ADC;SNR;ENOB;ADC Dynamic Testing
Date:	2001-07-10
Issue Date:	2009-09-22 11:38:08 (UTC+8)
Publisher:	國立中央大學圖書館
Abstract:	本論文中，我們提出一種架構在IEEE 1057，使用Histogram 及 FFT(The fast Fourier transform)方法，測試混合晶片內的類比數位轉換器(ADC)與訊號雜訊比(SNR)之量測方法。我們使用德州儀器(Texas Instruments) TMS320C62x EVM，來量測混合晶片(TLV320AIC22)內的類比數位轉換器(ADC)參數(Parameters)，推論一式由取樣點數(Sampling point)、取樣頻率(Sampling frequency)、取樣週期數(Sampling cycle)與訊號雜訊比(SNR)關係，並由曲線圖得有效位元(ENB)，符合在IEEE 1057測試混合晶片內的類比數位轉換器(ADC)有效位元(ENB)。 In this thesis, we will construct an IEEE 1057-1994 mixed signal circuit test library for mixed-signal SOC; use Histogram and FFT to measure. We will use Texas Instruments (TI) TMS 320c62x EVM, DSP processor and evaluation kit as the test vehicle. The test results include the relation between SNR and Number of Sampling, sampling frequency number of sampling cycle, ENOB.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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