| 摘要: | 本論文主要探討注入鎖定除頻器與四相位鎖相迴路之研究，在現今的毫米波頻段的收發機系統與雷達中，皆需要一個穩定且乾淨的振盪源，而本地振盪源通常以鎖相迴路來達成。因注入鎖定除頻器易操作在高頻，使注入鎖定除頻器普遍應用在毫米波頻段的鎖相迴路中的第一級除頻器，需要低功耗、高鎖定頻寬之特性，本論文主要針對高鎖定頻寬進行設計分析。
第二章介紹應用於鎖相迴路之K頻段四相位壓控振盪器，本次設計使用TSMC 0.18-μm¬ CMOS 的製程來完成此章節的電路設計。此章節會先簡介變壓器回授及耦合之理論，接著會對兩者架構模擬不同的耦合係數及匝數比對相位雜訊及輸出功率之影響。此外此章節探討數種耦合方式並對其耦合強度進行分析，並說明其優缺點，在其中挑選自我注入耦合來達成四相位壓控振盪器。此次電路設計成功實現出K頻段輸出訊號，分別使用變壓器回授及變壓器回授與耦合兩種電路設計並比較其電路性能，其中變壓器回授頻率可調範圍為22.94到24.5 GHz(1.56 GHz)，輸出功率大於-15.6 dBm。相位雜訊最好的值為-102 dBc/Hz控制電壓在1.5 V時，相位誤差及振幅誤差最大為5.5度及1.8 dB。變壓器回授及耦合之頻率可調範圍為21.61到22.71 GHz(1.1 GHz)，輸出功率大於-15.9 dBm。相位雜訊最好的值為-94.6 dBc/Hz控制電壓在1.3 V時，相位誤差及振幅誤差最大為8.2度及2.5 dB。
第三章使用電流再利用技術來完成 V 頻段注入鎖定除頻器之設計，此章節電路架構 利用兩級注入鎖定除頻器來完成除六除頻器之設計，最後使用 TSMC 90 nm GUTM CMOS 來完成此電路設計。由參考文獻中得知二次注入之增強鎖定頻寬技術。在此章節比較有二次注入兩種及無二次注入電路架構共有三種，從相關文獻進一步修正除頻器理論計算結果，提升鎖定頻寬理論計算結果與實驗結果的吻合性。驗證電路架構能有效的增強鎖定頻寬，並比較其鎖定頻寬。最後在電路設計裡也使用諧波增強技術來進一步加強除頻器之鎖定頻寬。量測時，注入訊號功率為 0 dBm，鎖定頻寬為 59.3 到 65.7 GHz，鎖定範圍為 6.4 GHz 相當於 7%的比例頻寬，電路的直流消耗為 14.3 mW。與模擬相比注入訊號功率為 0 dBm，鎖定頻寬為 55.8 到 64.2 GHz，鎖定範圍為 8.4 GHz 相當於 14 %的比例頻寬。模擬與量測中心頻率頻偏2.5 GHz鎖定頻寬減少2 GHz，如何除錯將在本章說明。
第四章為K頻段四相位鎖相迴路，電路使用TSMC0.18 μm互補式金屬氧化物半導體製程設計並實現，鎖相迴路包含變壓器回授四相位壓控振盪器、相位頻率偵測器、電荷幫浦、迴路濾波器、兩級注入鎖定除頻、兩級電流模式除頻器及三級單相位時序除頻器。在量測時分別對振盪器與迴路個別量測，量測時振盪器的頻率可調範圍增加 1 GHz振盪器增益增加1.8 GHz/V，導致迴路在無法鎖定會有迴路振盪的問題，會在本章節說明如何調整量測電壓使迴路鎖定，並探討迴路振盪的原因。模擬鎖定頻率範圍為22.02 GHz至23.49 GHz。量測鎖定範圍為22.189 GHz至24.02 GHz，相位雜訊最好的頻率為22.2- GHz在1 MHz頻率偏移時為-99 dBc/Hz，抖動為1 ps，相位雜訊最差的頻率為24 GHz在1 MHz頻率偏移時為-81.2 dBc/Hz，抖動為1.2 ps。抑制量小於-31.2¬¬ dBc，直流總功耗為90 mW
;This paper mainly discusses the research on the injection-locked frequency divider and the four-phase phase-locked loop. In today′s millimeter-wave transceiver systems and radars, a stable oscillator source is required, and the local oscillator source is usually a Phase-locked loop. In addition, the injection-locked frequency dividers (ILFD) are also employed in the millimeter-wave PLL due to their high speed and low DC power consumption, and the ILFD can be adopted as the first-stage frequency divider in the PLL.
The sond chapter introduces the K-band Quadrature voltage-controlled oscillator applied to the phase-locked loop. This design uses the TSMC 0.18 μm CMOS process to complete the circuit design of this chapter. This chapter first introduces the theory of transformer-feedback and transformer-coupled, and then simulate the effects of different coupling coefficients and turns ratio on phase noise and output power for the two architectures. In addition, this chapter discusses several coupling methods, analyzes their coupling strength, and explains their advantages and disadvantages. Among them, self-injection coupling is selected to achieve a four-phase VCO. This circuit design successfully realized the K-band output signal. Two circuits, transformer feedback, and transformer feedback and coupling were used to design and compare performance. The frequency of the transformer-feedback is 22.94 GHz when the control voltage is 0 V. The output power is 22.94 GHz. When the control voltage is 1.8 V, the frequency is 24.5 GHz, the output power is -15.6 dBm, and the frequency adjustable range is 1.5 GHz. The best value for phase noise is -102 dBc at 1.5 V control voltage. The maximum phase error and amplitude error are 5.5 degrees and 1.8 dB, and the output power of transformer feedback and coupling is -15.2 dBm when the control voltage is 0 V and the frequency is 21.61 GHz; when the control voltage is 1.8 V, the output power is - 22.71 GHz. 15.9 dBm, frequency adjustable to 1.1 GHz. The best value for phase noise is -94.6 dBc at the control voltage of 1.3 V. Phase error and amplitude difference up to 8.2 degrees and 2.5 dB
In Chapter 3, a current-reused technique is employed in a V-band ILFD. The circuit design of the presented ILFD is first presented with some theoretical calculations and simulations. Furthermore, a double-injection technique is also employed in the ILFD circuit design to enhance the locking range, and the ILFD is realized using a TSMC 90-nm CMOS VI process. As compared with prior art, the proposed ILFD features wide locking range and low DC power. With an input power of 0 dBm, the measured locking range is 59.3 to 65.7 GHz, locking range is 6.4 GHz, which corresponds to a proportional bandwidth of 7 %, and the DC consumption of the circuit is 14.3 mW. Compared to analog, the injected signal power is 0 dBm, the bandwidth is 55.8 to 64.2 GHz, and the lock range is 8.4 GHz, which corresponds to a proportional bandwidth of 14%. Simulate and measure the center frequency offset 2.5 GHz and lock the bandwidth by 2 GHz. How to debug will be explained in this chapter.
In Chapter 4,K-band Quadrature phase-locked loop. The PLL is using TSMC 0.18 μm CMOS process design and implementation. The building blocks of the PLL include a QVCO, a phase-frequency detector, a charge pump, a loop filter, two-stage ILFD and two-stage common-mode logic dividers and three-stage true single phase clocking dividers. In the VCO, the tunning range is increased by 2 GHz, and the gain of the oscillator is increased by 1.8 GHz/V, which causes the phenomenon of loop oscillation. How to debug will be explained in this chapter. The locking range from 22.02 GHz to 23.49 GHz, measurement locking range from 22.189 GHz to 24.02 GHz, phase noise -90 dBc/Hz at 1 MHz frequency offset, total DC power consumption 90 mW |
