本論文在提供實現單速率及多速率之低複雜度與高速有限脈衝響應數位濾波器(FIR)時的一些架構性設計的技術與方法，特別是應用在多速率多階內插有限脈衝響應數位濾波器(Interpolated FIR)時之設計上。首先，就一些已知對高速及低功率應用的單速率有限脈衝響應數位濾波器的技術提出概要介紹，接下來提出一些研究的成果，包括可變的濾波器階數的選擇、最佳化的濾波器階數分解和省記憶體及對稱濾波器對等等的技術，可以進一步對多速率多階有限脈衝響應數位濾波器架構獲得性能上的提升與降低其硬體複雜度。然後，基於典型有號數字(CSD)碼及內插有限脈衝響應數位濾波器設計所形成的通用型多速率多階有限脈衝響應數位濾波器將被提出。本論文也介紹一些對高速操作要求的設計，提出既可以增加硬體平行度又可以同時滿足低硬體複雜度的技巧與架構。 一個以TSMC 0.25um CMOS standard cell為製程的64-QAM基頻解調器之濾波器設計實例，證明使用所提出的方法可以將整體使用到的晶片面積減少約39%，適合低複雜度的應用。另外，對於高速的應用，此設計晶片執行速度可高達714MHz。最後，針對CDMA cellular應用的一個降頻8倍之多速率多階無乘法器的降頻器為實例，證明使用所提出的架構與方法可以比傳統方法降低整體晶片面積約70%，同時功率消耗也比使用單階多相位結構傳統方法降低約49%。 In this thesis, architecture design techniques for implementing single-rate and multirate high-speed finite impulse response (FIR) digital filters, with emphasis on the multirate multistage interpolated FIR (IFIR) digital filters are presented. Well-known techniques to achieve high-speed and low-power applications for the single-rate digital FIR architecture are summarized, followed by the introduction of variable filter order selection, optimal filter decomposition, memory-saving and mirror symmetric filter pairs techniques which offer further gains in both performance and complexity reduction for the multirate multistage digital FIR architecture. Then, a general-purpose multirate multistage digital FIR filter that is based on canonic signed digit (CSD) code representation and IFIR filter design methodology will be proposed. This thesis also describes some techniques by which sufficient parallelism for high-speed operation can be achieved, while simultaneously constraining the solution to have a small hardware implementation for these structures. A filter design example with TSMC 0.25um standard cell for 64-QAM baseband demodulator shows that the total gate count is reduced by 39% for low-complexity application. Moreover, for high-speed application, the chip can operate at 714MHz. Finally, a multirate multistage multiplierless decimators with decimation factor of eight is designed for the CDMA cellular application. It shows that the total gate count is reduced by 70% as compared with conventional approach. Moreover, the multirate multistage implementation can be reduced by 49% of the power consumption as compared to conventional single-stage implementation with only polyphase structure.
