本論文的主要目的是改善低漏電流和高崩潰電壓大面積矽偵測器的製程。研究成果顯示不同的製程和結構對偵測器漏電流及崩潰電壓均有顯著的影響。 首先，針對偵測器正面的氧化層、護層(passivation layer)和在偵測器背面使用砷離子佈植或POCl3預置擴散驅入技術來比較不同結構和製程對偵測器特性的影響。其實驗結果簡述如下: 1. 由於氧化層應力的關係，使得覆蓋氧化層的元件具有較高的漏電流和較低的崩潰電壓。 2. 同理由於應力的影響，有護層的偵測器具有較高的漏電流。但是，沒有護層的偵測器就無法預防水氣滲透的影響。 3. 偵測器背面使用POCl3預置擴散驅入會得到比較好的元件特性。 其次，我們也設計數種不同的測試元件(test-key)來討論防護圈(guard-ring)結構和圖形對元件漏電流和崩潰電壓的影響。實驗結果顯示防護圈可以增加元件崩潰電壓﹔在元件轉角部份，使用圓角會比使用直角好。 本大面積矽偵測器已通過歐洲粒子加速中心(CERN)的測試，並且獲得量產的機會。 In this thesis, techniques that could be used to reduce the leakage current and increase the breakdown voltage of the large-area single-sided silicon detector p+-i-n+ had been investigated. Five different processes had been used to fabricate the detectors and the resulted device characteristics were compared. For the front-side process of a detector, the breakdown voltage of a detector was significantly reduced by on the oxide covering the p+-strip, since the oxide layer had a large compressive stress. As to the backside of the detector, using the POCl3 diffusion process could result in a better n+-i junction and hence device performance than using As-implantation process. In addition, although the SiO2/Si3N4 passivation layer also increased the device leakage current due to its stress, but, the detector without passivation layer could not prevent moisture penetration which would increase the device leakage current and reduced the device reliability. By using test-keys on processed wafers, the effects of guard-rings on device performance had been studied. The guard-ring could be used to increase the device breakdown voltage, and the detector with rounded corners had the higher breakdown voltage and lower leakage current since the crowding electric-field around corner would be smoothed with rounded corners.
