寬資料範圍高速傳輸線之自適應關鍵技術;Key Technologies of Adaptability for Wide-Data Range of High-Speed Transmission Line

NCUIR > College of Electrical Engineering & Computer Science > Department of Electrical Engineering > Research Project > Item 987654321/91290

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/91290

Title:	寬資料範圍高速傳輸線之自適應關鍵技術;Key Technologies of Adaptability for Wide-Data Range of High-Speed Transmission Line
Authors:	鄭國興
Contributors:	國立中央大學電機工程學系
Keywords:	高速串列連結技術;向下相容性;低雜訊時脈產生;高速資料傳輸的訊號完整度;鎖相迴路;展頻時脈產生器;連續時間線性等化器;前饋式等化器;決策回饋等化器;資料與時脈回復電路;High-Speed Serial Link Technology;Downward compatibility;Low-Noise Clock Generation;Signal Integrity of High-Speed Data Transmission;Phase-Locked Loop;Spread-Spectrum Clock Generator;Continuous Time Linear Equalizer;Feed-Forward Equalizer;Decision-Feedback Equalizer;Clock and Data Recovery Circuit
Date:	2023-07-17
Issue Date:	2023-07-18 14:42:23 (UTC+8)
Publisher:	國家科學及技術委員會
Abstract:	本計畫探討高速傳輸介面相關之技術，在發展新穎的高速傳輸速率規格的同時，兼顧向下相容舊的傳輸速率規格，希望在電路應用方面有創新的突破，使我國相關技術之應用朝向多元化發展，在世界的舞台上大放異彩。
Relation:	財團法人國家實驗研究院科技政策研究與資訊中心
Appears in Collections:	[Department of Electrical Engineering] Research Project

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