近年來隨著數位影像應用的普及，一個能夠提供具有效率的表示方式及支援更多功能的靜態影像壓縮標準於焉而生。新一代的靜態影像壓縮標準JPEG2000與目前現存的影像壓縮標準比較起來，不只擁有更高的壓縮效率，還提供了多種功能，並可廣泛的應用在各種領域中。 本論文將針對JPEG2000靜態影像編碼系統作一分析與及其架構的設計。我們首先介紹JPEG2000編碼系統的編碼流程及基本原理，此系統主要包括三個主要功能方塊：離散小波轉換 (DWT)、純量量化以及採用EBCOT演算法的熵編碼。接著分析整個系統的複雜度，我們可經由實驗結果發現JPEG2000編碼系統的瓶頸在於EBCOT方塊編碼器。因此在本論文中，我們討論了幾種可以降低EBCOT編碼器運算時間的策略。在演算法的改良上，我們設計了兩種加速方法：CUPS (Clean Up Pass Skipping) 和PP (Pass Predicting) ，並經實驗證明了運用這兩種加速方法可以有效的降低EBCOT context產生器平均43%的運算時間。 另外，我們也完成了一個有效率的JPEG2000編碼系統硬體架構設計。在小波轉換的部分，提出了一個運用最簡運算單元來實現新一代小波(亦即lifting scheme)演算法的摺疊式架構，此架構具有較高的硬體使用率及較低的面積花費。對於純量量化器的設計，配合後續的EBCOT context產生器，我們採用與JPEG2000標準相容且最簡單的方式去實現。在EBCOT演算法方面，我們將前面所提出的加速演算法CUPS與PP加入，提出了一個硬體架構設計。本論文中所提出的加速演算法CUPS，僅需要一累加器去加總已編碼過的位元數目即可達成。加速演算法PP則需要額外的組合邏輯電路及兩塊記憶體來紀錄預測下一位元平面編碼掃描的情況。這些許的元件可使得整個EBCOT的編碼速度上更有效率。 Since the usage for digital imagery becoming popular in our world today, the still image compression standards that are able to provide the efficient representation and more features for different application are necessary. A new still image standard, JPEG2000, supplies not only higher compression performance but also various functionalities. Thus the commonly used standard, JPEG, can’t contend with. This thesis focuses on the analysis and architecture design for a JPEG2000 still image encoding system. We firstly introduce the fundamental concepts of JPEG2000 encoding system. It consists of three major block, DWT, scalar quantization, and EBCOT. Then we analyze this system with several experiments. Based on the experiment results, the bottleneck for JPEG2000, EBCOT, is found. In this regard, some strategies for decreasing the computation time of EBCOT are discussed. In order to improve the EBCOT algorithm, Clean Up Pass Skipping method (CUPS) and Pass Predicting method (PP) are proposed. We verify the CUPS and PP methods by completed simulation on VC++ environment and they can reduce the 43% clock cycles for EBCOT context modeling. Moreover, we achieve the efficient hardware architecture for the JPEG2000 encoding system. A new folded architecture for lifting-based DWT is presented. This design has the advantages of high hardware utilization and low area consumption. The architecture design for scalar quantization with VTQ is implemented. Using VTQ helps with reducing the computation time for EBCOT more efficiently than using DTQ. For the architecture design of EBCOT context modeling, proposed speed-improved methods are included. The CUPS method only needs an accumulator to sum up the number of coefficient-bits in a bitplane that have been coded in Pass1 and Pass2. The PP method requires extra combinational logic circuits and two predict tables to record the addresses when the Pass1 and Pass2 coding are needed. A few components can improve the speed efficiency.
