一個3.3V、8位元、每秒150百萬次取樣CMOS 類比數位轉換器 ;An 3.3V 8-bit 150MS/s Dual-channelTime-interleave Pipelined A/D Converter

NCUIR > College of Electrical Engineering & Computer Science > Graduate Institute of Electrical Engineering > Electronic Thesis & Dissertation > Item 987654321/9275

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/9275

Title:	一個3.3V、8位元、每秒150百萬次取樣CMOS 類比數位轉換器;An 3.3V 8-bit 150MS/s Dual-channelTime-interleave Pipelined A/D Converter
Authors:	羅仁鴻;Ren-Hong Luo
Contributors:	電機工程研究所
Keywords:	類比數位轉換器;ADC
Date:	2002-07-05
Issue Date:	2009-09-22 11:44:27 (UTC+8)
Publisher:	國立中央大學圖書館
Abstract:	摘要在本論文的主要目標是設計一個操作在3.3V之下、8位元、每秒150百萬次取樣(8bit,150Ms/s)的類比數位轉換器，以應用於RGB顯示器(LCD、CRT)及可攜式的儀表上。此類比數位轉換器採用平行管線化(Parallel- and-Pipelined)架構使硬體速度的需求度降低，同時可增加高速運算放大器的系統穩定時間(settling time)。此外，利用雙重取樣電路(double sampling)架構的取樣並保持電路相較傳統電路上在單位時間內有兩倍的取樣(sample)輸出。而在電路精確度的考量方面，而藉由重合一個位元的數位校正技術使得每一級(stage)的誤差容忍度有125毫伏(mV)；其中的電路之偏移誤差及所需比較器前級放大增益可藉由蒙地卡羅模擬以進行參數值估算。雙重取樣電路(double sampling)的原型晶片透過TSMC以0.25微米製程製作，面積約1.176mm×0.986mm，其量測結果與設計規格相符。而類比數位轉換器原型晶片透過TSMC以0.25微米製程製作，面積約3.136mm×2.534mm，功率消耗約467mW。 The subject of the thesis is to design an 8-bit, 150MS/s analog to digital converter(ADC) under a 3.3V supply. It can be applied in Gigabit Ethernet and RGB-to-LCD video signal processing interface circuits. This converter utilizes parallel-pipelined architecture to relax the hardware speed requirement. In addition, the Opamp can have a longer settling time under the same sampling rate. By means of double sample technique, the front end sample and hold (S/H) circuit has two times sampled data compared to traditional architectures. The coarse quantizer can tolerate 125mV comparator offset without overflow by digital error correction technique . The effect of process variation in the circuit will be estimated by Monte-Carlo simulation. The sample and hold circuit has been fabricated in TSMC 0.25μm CMOS process and occupies a chip area of 1.176mm0.986mm. The measurement result meets our targeted specifications. The simulation result of the analog to digital converter has 0.5LSB INL and 0.6LSB DNL. The whole ADC chip is fabricated in TSMC 0.25μm CMOS process and the die size is 3.136mm2.534mm.
Appears in Collections:	[電機工程研究所] 博碩士論文

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