| 摘要: | 本研究利用蕭特基 p 型氮化鎵閘極高電子遷移率電晶體架構之 650 V商用元件 GaN systems GS66508B，進行三大項目之探討與分析: (1)元件靜態特性的探討並著重在靜態導通電阻，(2)動態量測下，不同閘極開啟和汲極關閉電壓對於動態電阻的影響，(3) 動態量測下，不同閘極關閉和汲極關閉電壓對於動態電阻的影響。
元件動態開關量測所使用的平台為雙脈衝量測 (Double Pulse Test, DPT) 方法，主要雙脈衝量測的操作模式有電阻式負載和電感式負載，而本研究動態量測所使用的模式為電阻式負載，其模式可以減少因切換過程中寄生效應造成的震盪以得到更精準開關過程結果，其開關切換為硬切換且可以減少熱效應對動態電阻的影響。
對於元件靜態特性中，標準的閘極電壓開啟電壓為 6 V，其中發覺閘極電壓開啟電壓為 7 V時，靜態導通電阻相較於 6 V開啟有細微的改善；相反的在低的開啟電壓，元件特性有變差的趨勢。進一步對於動態量測下的閘極開啟電壓進行探討，發現在動態量測上此差異又更加明顯，其中發現在給予汲極高關閉電壓會使元件的臨界電壓向正偏移，導致需更正的閘極電壓方能使元件完全開啟。
另一方面，為了增加系統切換時的穩定性與安全性，當元件關閉時會給予負閘極電壓作為關閉，此負閘極電壓的對於元件的影響也是重要的討論事項。不同閘極關閉對於動態電阻的影響不盡相同，但整體可以觀察到越負的閘極關閉電壓會加劇動態電阻的增加。主要的物理機制有兩個可能，其一，在關閉時汲極的高偏壓會使的閘極和汲極之間形成高電場而產生碰撞游離(Impact Ionization)進而電子電洞對，而其中電洞原本可以扮演釋放陷阱 (detrap) 的角色，被負閘極關閉所吸引至閘極端，因而在多重效應加乘下元件的動態電阻會極劇增加；其二，在元件關閉時給予閘極負偏壓，會使的原本在 p-GaN 層中的電洞被吸引至閘極電壓，而元件開啟瞬間因原本在 p-GaN 層中的電洞無法立即恢復，造成元件臨界電壓向右偏移的情況發生，使的動態電阻極劇增加。
;This study utilizes a Schottky p-type GaN high electron mobility transistor (HEMT) structure, the GaN Systems GS66508B, 650 V commercial device, for in-depth investigation and analysis. The research focuses on three main aspects: (1) exploring the static characteristics of the device with an emphasis on static on-state resistance, (2) under dynamic measurements, analyzing the effect of different gate turn-on and drain turn-off voltages on dynamic on-state resistance, and (3) under dynamic measurements, analyzing the effect of different gate turn-off and drain turn-off voltages on dynamic on-state resistance.
The platform used for dynamic measurements in this study is the Double Pulse Test (DPT) method, which can be operated in either a resistive load or an inductive load mode. This research employs the resistive load mode to reduce oscillations caused by parasitic effects during switching and obtain more accurate measurement results. The switch is hard-switched to minimize the influence of thermal effects on resistance.
Regarding the static characteristics of the device, the standard gate voltage turn-on voltage is 6 V. However, it was observed that a gate voltage turn-on voltage of 7 V slightly improves the static on-state resistance compared to 6 V, while lower turn-on voltages result in deteriorated device performance. Further investigation into the gate turn-on voltage under dynamic measurements reveals a more pronounced difference. Providing a higher drain turn-off voltage shifts the device′s threshold voltage to the right, requiring a higher gate voltage to fully turn on the device.
On the other hand, for system stability and safety during switching, negative voltages are applied to the device when turning off. The impact of these negative gate voltages during device turn-off is also an important aspect of the discussion. It was found that different gate turn-off voltages have varying effects on dynamic on-state resistance. Generally, more negative gate turn-off voltages exacerbate the degradation of dynamic on-state resistance due to two main internal mechanisms. Firstly, the high bias between the drain and source during turn-off leads to high electric fields and impact ionization, generating electron-hole pairs. The holes, which could have played a role in detraping, are attracted to the negative gate voltage, leading to severe degradation of dynamic on-state resistance through a multiplication effect. Secondly, applying a negative gate bias during device turn-off causes holes in the p-GaN layer to be attracted to the gate voltage. When the device is turned on again, these holes cannot immediately return to their original positions, resulting in a rightward shift of the device′s threshold voltage and causing significant degradation of dynamic on-state resistance. |
