在此篇論文裡，我們介紹了使用超取樣方法的全數位式資料回復技術及電路架構應用在高速序列傳輸。一些重要效能和設計參數都會被分析及公式化以便不同的設計參數可以設計符合不同的規格。整個電路的架構非常規律和適合以標準庫存元件(standard-cell)的流程完成，因此使它非常適合當做軟矽智產(Soft Silicon Intellectual Property)。我們更進一步的建立一個模組產生器，它可以自動產生verilog語言。它亦可自動產生設計參數去處理超取樣架構以符合不同的規格。最後一個利用模組產生器的設計範例，將以TSMC 0.35um 1P4M的數位製程予以實現。此設計的最快工作效率可以達到1.9Gbps，且在3.3V的電壓下功率消耗為112.2mW。若無preamble的電路其效率可達2.09Gbps。 In this thesis, we introduce the technique and circuit architecture for the all-digital data recovery of high-speed serial link using an oversampling method. Several key performance and design parameters indices are analyzed and formulated so that different specification can be designed with different design parameters. The overall architecture is very regular and hence very suitable for standard cell implementation flow that makes it very suitable as a Soft Silicon Intellectual Property. Furthermore, we establish a module generator which can generate the design in verilog code automatically. It can automatically generate the design parameters to deal with the oversampling architecture to meet different specifications. Finally, a design example generated by the module generator is implemented in a cell-based design method using the TSMC 0.35 1P4M cell library. The maximum performance of the design can reach 1.9 Gbps with power consumption of 112.2mW at 3.3V. Without preamble circuit, the performance can reach 2.09 Gbps.
