56/28 Gb/s雙模式高速串列收發器之關鍵技術設計與實現;Design and Implementation of Key Techniques in 56/28 Gb/S Dual-Mode High-Speed Serial Transceiver

NCUIR > College of Electrical Engineering & Computer Science > Department of Electrical Engineering > Research Project > Item 987654321/93231

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/93231

Title:	56/28 Gb/s雙模式高速串列收發器之關鍵技術設計與實現;Design and Implementation of Key Techniques in 56/28 Gb/S Dual-Mode High-Speed Serial Transceiver
Authors:	鄭國興
Contributors:	國立中央大學電機工程學系
Keywords:	高速串列連結技術;低雜訊時脈產生;高速資料傳輸的訊號完整度;鎖相迴路;展頻時脈產生器;連續時間線性等化器;前饋式等化器;決策回饋等化器;資料與時脈回復電路;High-Speed Serial Link Technology;Low-Noise Clock Generation;Signal Integrity of High-Speed Data Transmission;Phase-Locked Loop;Spread-Spectrum Clock Generator;Continuous Time Linear Equalizer;Feed-Forward Equalizer;Decision-Feedback Equalizer;Clock and Data Recovery Circuit
Date:	2024-01-26
Issue Date:	2024-01-29 16:50:11 (UTC+8)
Publisher:	科技部
Abstract:	本計畫探討新世代的高速串列傳輸介面，根據國際組織預期之規格，發展適用於新資料格式的高速串列傳輸關鍵技術，希望在電路應用與可靠度上有進一步的突破，使我國也能具備符合新版規格的高速串列傳輸，在與世界的競爭中創造優勢。
Relation:	財團法人國家實驗研究院科技政策研究與資訊中心
Appears in Collections:	[Department of Electrical Engineering] Research Project

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