應用於自旋轉移矩-磁阻式隨機存取記憶 體修剪及測試之可編程內建自我測試架構;Programmable Built-In Self-Test Scheme for the Trimming and Testing of STT-MRAMs

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題名:	應用於自旋轉移矩-磁阻式隨機存取記憶體修剪及測試之可編程內建自我測試架構;Programmable Built-In Self-Test Scheme for the Trimming and Testing of STT-MRAMs
作者:	潘哲維;Pan, Zhe-Wei
貢獻者:	電機工程學系
關鍵詞:	自旋轉移矩-磁阻式隨機存取記憶體;測試;修剪;內建自我測試;可編程內建自我測試;STT-MRAM;testing;trimming;BIST;PBIST
日期:	2023-08-21
上傳時間:	2024-09-19 17:09:03 (UTC+8)
出版者:	國立中央大學
摘要:	在各種非揮發性記憶體技術中，由於自旋轉移矩磁阻式隨機存取記憶體(STT-MRAM)具有較低的讀/寫延遲、更好的耐用性和數據保留能力，因此有望成為下世代的先進記憶體技術。此外，STT-MRAM也被視為適用於數據密集型應用的記憶體內運算架構的有力選擇。然而STT-MRAM存在低隧道磁阻和容易受到熱擾動的問題，且磁隧道結元件的製造引入了新的缺陷。這些因素共同導致STT-MRAM在進行量產時面臨著測試和良率的兩大挑戰。　在論文的第一部分中，我們提出了一種針對STT-MRAM 記憶體內運算架構的修剪技術。這項技術在設計階段基於不同修剪電阻值相關的機率密度函數產生其對應之修剪電阻，並使用查找表來儲存預期的錯誤數據。在量產測試階段，通過對邊界修剪電阻進行修剪測試可以得到故障位計數。隨後通過比較故障位計數與查找表中的預期錯誤數，選擇合適的參考電阻。由於僅透過查找表產生修剪電阻，因此其複雜度為O(1)。相對於現有的二分搜尋法，此修剪技術在記憶體及記憶體內運算模式下分別減少約45.77％和99.99％的測試時間。此外，與未使用修剪時相比，它還能提高至少8％的變異容忍度。　　在論文的第二部分中，我們提出了一種針對STT-MRAM的可測試性(DFT)增強測試方案。在測試演算法中會利用DFT調整讀取操作時的讀取電流，以強化可檢測的缺陷尺寸範圍，從而提高測試品質。模擬結果顯示，在具有可調整讀取電流的17.5N測試演算法中，相對於傳統測試演算法可以覆蓋約19倍的缺陷尺寸。同時我們還提出了一種減少測試複雜度並優化測試品質的方法，將測試演算法的測試複雜度從17.5N減少到7N，且達到約17倍的缺陷尺寸覆蓋率。與傳統演算法相比，在相似的複雜度水平下，所提出的演算法相較於過去的方案提升至少2.6倍的測試品質。　　在論文的第三部分中，我們基於STT-MRAM提出了一種可編程的內建自我測試(PBIST) 架構。提出的PBIST架構可以同時支援修剪、生產和DFT增強測試的功能。在PBSIT當中引入了全新的指令集，利用行進式測試的對稱特性，從而減少PBIST中微指令碼的尺寸。相對於現有的方法，相對於傳統指令集，所提出的指令集僅需約52.7％的微指令碼位元數就能實現行進式和非行進式測試，例如，March Y、March C+、March SS、Galloping、 Walking以及Butterfly。我們使用TSMC 40nm CMOS標準單元設計了一個256Kx256位的MRAM PBIST，以支援6位修剪解析度的修剪測試。PBIST的面積成本約為14654μm2，操作頻率達 2GHz。;Among various non-volatile memory technologies, spin-transfer torque magnetic random access memory (STT-MRAM) is a promising memory for advanced technology nodes due to its lower read/write latency, better durability, and data retention. Furthermore, STT-MRAM has been considered as a candidate of in-memory computing (IMC) architecture for data-intensive applications. However, STT-MRAM has the inherent properties of low tunneling magnetoresistance (TMR) and thermal disturbance. Also, the fabrication of the magnetic tunnel junction (MTJ) device induces new defects. Those cause that the testing and yield enhancement are two key challenges for the volume production of STT-MRAMs. In the first part of this thesis, we propose a trimming technique for STT-MRAM IMC memories. The trimming technique uses the lookup table to store the expected error number with respect to different trimming resistances in terms of simulation probability distribution in the design phase. In the production test phase, a trimming test is executed for the boundary trimming resistance and the fail bit counts can be obtained. Then, we can select an appropriate reference resistance by comparing the fail bit counts with the expected error number in the lookup table. Since only the boundary trimming resistance is used for the trimming test, the trimming test complexity is O(1). In comparison with existing binary search approach, the proposed trimming technique can achieve about 45.77% and 99.99% test time reduction in memory mode and computing mode, respectively. Furthermore, compared to the scenario without trimming, it can also enhance variation tolerance by up to 8%. In the second part of this thesis, we propose a design-for-testability(DFT)-enhanced test scheme for STT-MRAMs. In a test algorithm, the read current of a read operation can be adjusted through DFT circuits to extend the detectable range of defect size such that the test quality is improved. Simulation results show that a 17.5N test algorithm with adjustable read current can cover about 19 times of defect size than conventional test algorithm without read current adjusting. A test complexity and test quality optimization approach is proposed to reduce the test complexity. The 17.5N test algorithm can be reduced to 7N and achieve about 17 times of defect size coverage. Compared to traditional algorithms, the proposed algorithm achieves at least 2.6 times higher test quality at similar complexity levels. In the third part of this thesis, we propose a programmable built-in self-test (PBIST) scheme for STT-MRAMs. The PBIST scheme can support the trimming test, production test, and DFTenhanced test. A novel instruction set is proposed to reduce the size of microcode of the PBIST by taking advantage of the symmetric characteristics of March tests. In comparison with existing works, the proposed instruction set can realize march and non-march tests, such as March Y, March C+, March SS, Galloping, Walking, and Butterfly, using only about 52.7% microcode bits. We design a PBIST for 256Kx256-bit MRAM using TSMC 40nm CMOS standard cells to support the trimming test for 6-bit trimming resolution. The area cost of the PBIST is about 14654μm2 at the operation frequency of 2GHz.
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