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    題名: BB-YOLO:基於二值主幹網路之 YOLO 物件偵測硬體加速器設計與實現;BB-YOLO : Design and Implementation of Hardware Accelerator for YOLO Object Detection Network Based on Binary Backbone
    作者: 陳治嘉;Chen, Chih-Chia
    貢獻者: 資訊工程學系
    關鍵詞: 二值卷積;物件偵測網路;FPGA;硬體加速器
    日期: 2024-07-23
    上傳時間: 2024-10-09 17:00:12 (UTC+8)
    出版者: 國立中央大學
    摘要: 深度學習在物件偵測領域展現過人成效,然而其涉及龐大運算量與記憶體佔用,難以運用在計算資源受限且需即時運算之邊緣裝置場域上。為了解決該問題,本論文提出基於二值主幹網路之YOLO物件偵測網路,其主幹網路為二值卷積運算為主之ReActNet,該策略大幅減少模型參數量與模型大小,並將該網路更進一步透過階層式模組化設計方法,提出具有彈性架構之BB-YOLO二值主幹網路物件偵測硬體加速器,並加入管線化設計與定點運算取代浮點數運算,以提升神經網路推論速度並減少硬體資源使用量。根據實驗結果分析,該硬體加速器單一影像偵測所需時間為9.0967µs,相較於具有圖形處理器之主機平台,展現出優異推論加速效果。本論文提出之BB-YOLO硬體加速器不僅具有彈性架構特點,同時在推論上展現即時性,從而提供在硬體資源有限場域中實現即時物件偵測的一種解決方法。

    ;Deep learning has demonstrated remarkable performance in the field of object detection. However, its extensive computational and memory requirements make it challenging to deploy on edge devices with limited computing resources requiring real-time operations. To address this issue, this paper proposes a YOLO-based object detection network based on a binary backbone network. The backbone network primarily utilizes binary convolution operations from ReActNet, significantly reducing model parameters and size. Furthermore, a flexible architecture BB-YOLO is introduced using a hierarchical modular design approach. Additionally, a hardware accelerator for BB-YOLO integrates pipelined design and fixed-point arithmetic, replacing floating-point operations to enhance neural network inference speed and reduce hardware resource usage. Experimental results show that the hardware accelerator requires 9.0967μs for single image detection, demonstrating excellent inference acceleration performance compared to a computer server with Graphics Processing Unit. The proposed BB-YOLO hardware accelerator not only features a flexible architecture but also enables real-time inference. Consequently, it offers a viable solution for real-time object detection in hardware-constrained environments.
    顯示於類別:[資訊工程研究所] 博碩士論文

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