以高介電常數鈍化層提高氮化鎵高電子遷移率電晶體崩潰電壓之研究;Breakdown Voltage Enhancement of GaN HEMTs Using High-k Passivation Layers

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題名:	以高介電常數鈍化層提高氮化鎵高電子遷移率電晶體崩潰電壓之研究;Breakdown Voltage Enhancement of GaN HEMTs Using High-k Passivation Layers
作者:	洪子鈞;Hong, Zih-Jyun
貢獻者:	電機工程學系
關鍵詞:	氮化鎵
日期:	2024-03-26
上傳時間:	2024-10-09 17:00:21 (UTC+8)
出版者:	國立中央大學
摘要:	本研究以p 型閘極氮化鎵高電子遷移率電晶體為研究標的，在做完金屬閘極後，分別沉積不同組合的雙層鈍化層，包含樣品A 氧化鋁加氧化矽 (Al2O3 + SiO2)、樣品B 氮化矽加氧化矽(Si3N4 + SiO2)以及樣品C 氧化鋯加氧化矽(ZrO2 + SiO2)，以改變鈍化層的介電常數來提高元件的崩潰電壓，並藉由量測來比較不同鈍化層的p 閘極型氮化鎵高電子遷移率電晶體特性。元件直流特性方面，三個樣品的ID,off 分別為樣品A = 3.1×10-6 mA/mm、樣品B = 1.44×10-5 mA/mm、樣品C = 3.61×10-7 mA/mm，由於樣品A (Al2O3)及C (ZrO2)均使用ALD 沉積，因此其漏電流都比使用PECVD 沉積的樣品B (Si3N4)來的低，很可能是由於後者表面有電漿轟擊造成的缺陷；其中樣品C (ZrO2)的整體表現最佳，能夠有效減少漏電流，同時在低漏電流的情況下還能夠維持1.99 mΩ-cm2 的導通電阻。在動態特性部分，我們以施加偏壓前後之通道電阻比值來表達，在Vgsq = -15 V 下，三個樣品的動態電阻分別為1.19、1.13、1.07，可以證明樣品C (ZrO2)的製程能夠較有效減少表面缺陷，減少電子被捕捉的機會。因為Drain Lag 特性主要由緩衝層來主導，而本研究所使用磊晶片為了提高崩潰電壓，在緩衝層內有碳摻雜，使得三個樣品在Vdsq = 100 V 下，動態電阻分別提升至6.67、3.80、4.55，表示電子被緩衝層捕捉的現象相當嚴重。元件崩潰特性是本研究的重點之一，預期透過介電質的極化來分散電場進而減緩撞擊游離的發生，以提升崩潰電壓。三個樣品崩潰電壓分別為 1185 V、955 V、1670 V，可以證明使用高介電常數鈍化層確實可提高元件崩潰電壓。未來，在磊晶結構設計時可以透過強化通道下位障層(back barrier)之效果，降低通道電子被緩衝層捕捉的現象，提升元件動態特性。;This study focuses on the development of p-GaN gate high-electron-mobility transistors (p-GaN gate HEMTs) for 1200 V applications. Three different duallayer passivation films were investigated, i.e. Sample A with aluminum oxide and silicon oxide (Al2O3+SiO2), Sample B with silicon nitride and silicon oxide (Si3N4+SiO2), and Sample C with zirconium oxide and silicon oxide (ZrO2+SiO2). The goal is to increase the breakdown voltage of the devices using high dielectric constant passivation layers. The off-state drain current (ID, off) is 3.1×10-6 mA/mm, 1.44×10-5 mA/mm, and 3.61×10-7 mA/mm for Sample A. B, and C, respectively. The difference in the off-state current could be attributed to the different deposition processes and dielectric materials of the passivation films. Since the passivation layers of Sample A (Al2O3) and C (ZrO2) were deposited by atomic layer deposition (ALD), while the Si3N4 film on Sample B was deposited by plasma-enhanced chemical vapor deposition (PECVD), which might result in plasma damages on the sample surface. Among these three samples, Sample C (ZrO2) exhibited the best performance with a specific on-resistance as low as 1.99 mΩ-cm2 and low drain/gate leakage current. As to the dynamic characteristics, the dynamic on-resistance normalized to unstressed condition was measured after an off-state Vgsq up to -15 V. The dynamic resistance for Samples A, B, and C was 1.19, 1.13, and 1.07, respectively. Sample C (ZrO2) demonstrated more effective reduction in surface defects, minimizing the probability of electron trapping. Since the drain-lag characteristic is also affected by the buffer layer, which was doped with carbon to increase its resistance and breakdown voltage, the dynamic resistances after stressed by a Vdsq of 100 V, increased to 6.67, 3.80, and 4.55 for Sample s A, B, and C, respectively, indicating a pronounced trapping effect in the buffer layer. Device breakdown characteristic, one of the focuses of this study, was measured to investigate the effect of dielectric polarization on impact ionization induced leakage current. The breakdown voltages for the three samples were 1,185 V, 955 V, and 1,670 V, respectively, confirming that high dielectric constant passivation layers can indeed increase the breakdown voltage of the devices through dielectric polarization. In the future, adding a back barrier under the channel to reduce the trapping of channel electrons by the carbon acceptors in the buffer, might further improve the dynamic characteristics.
顯示於類別:	[電機工程研究所] 博碩士論文

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