具資料速率偵測機制之 3~8 Gbps 頻寬可調自適應等化器;A 3 ~ 8 Gbps Adjustable Bandwidth Adaptive Equalizer With Data Rate Detection Mechanism

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题名:	具資料速率偵測機制之 3~8 Gbps 頻寬可調自適應等化器;A 3 ~ 8 Gbps Adjustable Bandwidth Adaptive Equalizer With Data Rate Detection Mechanism
作者:	徐伃葶;Syu, Yu-Ting
贡献者:	電機工程學系
关键词:	等化器;資料速率偵測機制;寬操作速率;Equalizer;Data Rate Detector;Wide data rate
日期:	2024-07-26
上传时间:	2024-10-09 17:13:43 (UTC+8)
出版者:	國立中央大學
摘要:	近年來隨著製程發展日益精進，資料傳輸量越來越大且資料傳輸速率日漸提升，促使高速串列傳輸介面不斷推陳出新，而舊的傳輸介面仍存在市場上且持續流通。為了使新舊傳輸介面能夠相容，本論文設計一具資料速率偵測機制可操作於 3~8 Gbps 的頻寬可調變自適應等化器，使其能應用於 PCIe 3.0 以及 USB 3.0 的傳輸介面。由於電路的操作速率為一範圍，若是利用時脈與資料回復電路 (Clock and Data Recovery Circuit, CDR)來進行資料速率的判斷，則電路功耗勢必會上升。考量電路的功耗以及面積成本，所以提出了資料速率偵測機制對資料速率進行判斷，判斷完成後會對等化器的頻寬進行調整，使調頻後的等化器有利於補償更多的通道損失。在資料速率偵測機制方面，為了減少 PVT 變異對資料速率判斷時的影響，加入 PVT 偵測電路對資料速率偵測機制進行校正。 ;In recent years, with advances in processes, data transfer volumes have increased significantly and transmission speeds have continued to rise. This trend has driven continuous innovation in high-speed serial transmission interfaces, while older interfaces still remain in the market and circulate. To enable compatibility between new and old transmission interfaces, this thesis designs a bandwidth-adjustable adaptive equalizer with a data rate detection mechanism capable of operating in the range of 3 to 8 Gbps. This allows its application in transmission interfaces such as PCIe 3.0 and USB 3.0. Due to the operational rate variability of circuits, using a Clock and Data Recovery Circuit (CDR) for data rate determination inevitably increases circuit power consumption. Considering power and area costs, a data rate detection mechanism is presented to detect data rates. Upon detection, the bandwidth of the equalizer will be adjusted, enhancing its capability to compensate for more channel losses. To mitigate the impact of PVT variations on data rate determination, a PVT detection circuit is integrated to calibrate the data rate detection mechanism.
显示于类别:	[電機工程研究所] 博碩士論文

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