| 摘要: | 此篇論文使用台灣積體電路製造股份有限公司 (tsmcTM) 0.18-µm CMOS製程，設計應用於第五代和第六代通訊的三顆晶片，此三顆晶片分別為應用於n77頻段之差動堆疊式功率放大器、應用於X頻段之差動堆疊式功率放大器、應用於X頻段之連續B類堆疊式功率放大器。
第二章分成兩部份：第一顆晶片為應用於n77頻段之兩級差動堆疊式功率放大器，此設計採用基於磁耦合變壓器之堆疊式架構，同時使用電阻式自偏壓方法減少電路不穩定性和複雜性。量測結果顯示在n77頻段內最大傳輸增益為13.39 dB，操作頻帶為3.6 ~ 4.4 GHz，頻帶飽和輸出功率為22 ~ 23.1 dBm，1-dB增益壓縮點輸出功率為12.9 ~ 14.9 dBm，最高功率附加效率為6.9 ~ 9.3 %，晶片面積為3.77 mm2 (2.85 mm×1.32 mm)。第二顆晶片為應用於X頻段之兩級差動堆疊式功率放大器，此設計採用基於磁耦合變壓器之堆疊式架構，使用獨立閘極電壓，操作頻帶為7.7 ~ 8.3 GHz，最大傳輸增益為12.2 dB，頻帶飽和輸出功率為20.2 ~ 22.6 dBm，最高功率附加效率為6.2 ~ 8.6 %，1-dB增益壓縮點之輸出功率為13.6 ~ 15.6 dBm，晶片面積為2.1 mm2 (2.08 mm×1.02 mm)。
第三章的第三顆晶片為應用於X頻段之兩級連續B類堆疊式功率放大器，此設計輸出利用輸出端共振腔達到二倍頻開路之效果，以抑制二次諧波和增加頻寬。在功率級堆疊式電晶體間加入一米勒電容以達到特性的最佳化，其操作頻寬包含的頻段為6.2 – 7.8 GHz，最大傳輸增益為12.5 dB，頻帶飽和輸出功率為20.3 ~ 22.6 dBm，最高功率附加效率約為8.7 ~ 14.5 %，1-dB增益壓縮點之輸出功率為14.5 ~ 16.2 dBm，晶片面積為1.85 mm2 (1.61 mm × 1.15 mm)。
;This thesis proposed three power amplifiers (PAs) which were designed and fabricated in in tsmcTM 0.18-µm CMOS technologies to design three chips for 5th and 6th generation communication system applications. These three chips are a differential stack power amplifier for n77 band, a differential stack power amplifier for X band, and a continuous mode class B stack power amplifier for X band.
Chapter 2 is divided into two parts. The first chip presents a two-stage differential stacked power amplifier for n77 band. This design adopts a stacked structure based on magnetically coupled transformers, and uses resistive self-biasing to reduce circuit instability and complexity. The measurement results show that the maximum power gain in the n77 band is 13.39 dB, the operating band is 3.6 ~ 4.4 GHz, the saturation output power is 22 ~ 23.1 dBm, the 1-dB gain compression point output power is 12.9 ~ 14.9 dBm, the maximum PAE is 6.9 ~ 9.3%, and the chip area is 3.77 mm2 (2.85 mm × 1.32 mm). The second chip presents a two-stage differential stacked power amplifier for X-band. This design adopts a stacked structure based on magnetically coupled transformers and uses independent gate voltages. The operating band is 7.7 ~ 8.3 GHz, the maximum power gain is 12.2 dB, the band saturation output power is 20.2 ~ 22.6 dBm, the maximum PAE is 6.2 ~ 8.6 %, the output power at 1-dB gain compression point is 13.6 ~ 15.6 dBm, and the chip area is 2.1 mm2 (2.08 mm×1.02 mm).
In Chapter 3, the third chip presents a two-stage continuous class-B stacked power amplifier for X-band. The output of this design uses the resonator at the output port to achieve a dual-frequency open circuit effect to suppress the second harmonic and increase the bandwidth. A Miller capacitor is added between the power stage stacked transistors to optimize the characteristics. Its operating bandwidth includes 6.2 – 7.8 GHz, the maximum power gain is 12.5 dB, the band saturation output power is 20.3 ~ 22.6 dBm, the highest PAE is about 8.7 ~ 14.5 %, and the output power at the 1-dB gain compression point is 14.5 ~ 16.2 dBm. The chip area is 1.85 mm2 (1.61 mm × 1.15 mm). |
