奈米CMOS晶片內序列傳輸之接收器; Nanometer CMOS On Chip Serial Link Receiver

NCU Institutional Repository > 資訊電機學院 > 電機工程研究所 > 博碩士論文 > Item 987654321/9875

jsp.display-item.identifier=請使用永久網址來引用或連結此文件: http://ir.lib.ncu.edu.tw/handle/987654321/9875

题名:	奈米CMOS晶片內序列傳輸之接收器;Nanometer CMOS On Chip Serial Link Receiver
作者:	蕭儒遠;Ju-Yuan Hsiao
贡献者:	電機工程研究所
关键词:	奈米;接收機;Receiver;Nanometer
日期:	2005-07-05
上传时间:	2009-09-22 11:58:32 (UTC+8)
出版者:	國立中央大學圖書館
摘要:	在系統單晶片中，設計晶片中的拉線電路十分困難，因為在模組之間的拉線通常會長到5000mm，而且拉線損耗的動態能量在整體晶片中更佔了30%。此論文將從設計者的觀點描述未來拉線的重要性和並提出新的拉線電路。因此，我們提出兩種特殊的架構來改善拉線電路的能量損耗和速度，分別是電流感應電路和並列轉序列電路。首先，我們提出序列式的傳輸應用在晶片內拉線電路上，這種傳輸的好處是很低的拉線複雜度，同時也可比傳統的插入訊號放大器方式省下近60%能量損耗。另外，我們也提出利用電流感應的技術，這種技術可以提供接收端的阻抗匹配同時也達到較高的傳輸頻寬，此外這種技術應用比起電壓感應的技術更加適用於在序列式傳輸上。最後，我們提供一個模組分析的工具，可以根據製程的參數、資料傳輸的特性和拉線的長度，提供並且幫助我們設計符合我們所需求的電路。最後，我們分別採用台積電130微米 1P8M CMOS和聯電130微米 1P8M CMOS製程實作出晶片並達到資料速度5Gbps。 In SOC system design using nano scale CMOS process, it is difficult to design interconnects for low power and high speed. It is because modules may use global interconnects with length up to 5000mm to exchange signals. Besides, 30% of the chip's dynamic power was consumed by interconnects. In this thesis, we first describe the importance of wires in the future nano scale process and the trend of interconnect link circuit and from designer’s point of view. Therefore, we propose two novel schemes to improve the power and speed of interconnect links: current sensing technique and parallel to serial link circuit. First, we propose a serial link technique to reduce power consumption without decreasing throughout. Parallel to serial links has low complexity in routing area and save power consumption up to 60% than optimal repeater insertion method. Besides, we also propose current sensing technique for long interconnects. The advantages of current sensing techniques are: First, current sensing provides suitable impedance in receiver side to match the interconnect impedance which provides higher bandwidth in signal transmission. Second, current sensing amplifier is more suitable than voltage sensing in parallel to serial technology. Finally, we develop a power model of interconnect link. According to technology parameter, data activity, and interconnect length, power model will help to decide the exact interconnect parameters to satisfy the performance requirements. Finally, we implement two chips in tsmc 130nm and UMC 130nm to show the performance which data rate can up to 5Gbps.
显示于类别:	[電機工程研究所] 博碩士論文

文件中的档案:

档案	大小	格式	浏览次数

在NCUIR中所有的数据项都受到原著作权保护.

社群 sharing

数据加载中.....