一個新型全數位式高解析度可變責任週期之同步複製延遲電路; A New All-Digital High-Resolution Synchronous Mirror Delay with Arbitrary Duty Cycle

NCUIR > College of Electrical Engineering & Computer Science > Executive Master of Electrical Engineering > Electronic Thesis & Dissertation > Item 987654321/9947

Please use this identifier to cite or link to this item: http://ir.lib.ncu.edu.tw/handle/987654321/9947

Title:	一個新型全數位式高解析度可變責任週期之同步複製延遲電路;A New All-Digital High-Resolution Synchronous Mirror Delay with Arbitrary Duty Cycle
Authors:	許齊發;Chi-fa Hsu
Contributors:	電機工程研究所碩士在職專班
Keywords:	同步電路;同步複製延遲電路;Synchronous Clock;Synchronous Mirror Delay;SMD
Date:	2009-01-08
Issue Date:	2009-09-22 12:01:40 (UTC+8)
Publisher:	國立中央大學圖書館
Abstract:	當系統晶片所使用之頻率愈來愈高時，同步電路效能之好壞即會影響整體電路動作是否正常。因此，對於訊號同步電路亦愈重視。故有鎖相迴路（Phase-Locked Loop，PLL）及延遲迴路（Delay-Locked Loop，DLL）皆被廣泛運用於系統晶片內，但此兩種電路則需考慮幾項問題。第一為此兩種皆為閉迴路系統，故會有頻寬問題，需利用電容來增加電路之穩定性。第二點為此些電路需花幾百個時脈週期以上才能鎖定，於鎖定過程中需較大之功率消耗。有鑒於此，因而發展出同步複製延遲電路（Synchronous Mirror Delay，SMD）以降低鎖定週期及功率消耗。但傳統式數位同步複製延遲電路有三項主要之缺點：其一為輸入訊號責任週期受到限制。其二為靜態相位誤差太大。其三就是電路會受到輸出負載改變之影響，使傳統式數位同步複製延遲電路只能運用於記憶體模組。為使同步複製延遲電路能運用於更廣的範圍，因而提出一個新的數位同步複製延遲電路，本篇論文會針對上述之缺點做改善，並且輸入與輸出訊號間的靜態相位誤差≦16.6 ps，輸入訊號的責任週期可以任意調變(20%~80%)，並以TSMC 0.13μm製程實現晶片，可操作頻率為222~800MHz。當頻率為800MHz時的功率消耗為5.14mW、靜態相位誤差為8.07ps。核心電路的面積(不含I/O PAD)為0.015mm2。本篇論文後半段有佈局後之模擬結果，以證明的確可以改善上述之缺點。 When the frequency of system clock is increasing in System-On-Chip (SoC), the efficiency of clock synchronization would affect the normal motion of the entire circuit. Therefore both Phase-locked Loop (PLL) and Delay-Locked Loop (DLL) are widely used in SoCs for many synchronization-dependent systems in order to suppress the clock skew. However, some issues shall be considered while using these two circuits. First of all, since it is closed-loop system, there would be problem of bandwidth, it rely on capacitance to increase the stability of the circuit. Secondly, these circuits would need hundreds clock cycles before locked, which consumed larger power during long locking process. Consequently, synchronous mirror delay (SMD) is developed to reduce lock cycle and power consumption, and to replace PLL and DLL. However, there are three major defects in conventional SMD. Start with; the duty cycle for input signal is restricted. Next, the static phase error is large after locking. Finally, circuits would be affected by the change in output load, which makes the conventional synchronous mirror delay can be only used in memory module. In order to enable synchronous mirror delay to be used in a wider range, a high precision fast locking arbitrary duty cycle clock synchronization circuit is introduced, which not only fix the defects of conventional SMD, but also gain the phase error between the input signal and output signal is less than 16.6 ps. And the tuning range of input signal’s duty cycle is 20% ~80%. The test chip is fabricated in a 0.13-μm, and the operating frequency is between 222~800MHz. It consumes 5.14mW and static phase error is 8.07ps when the frequency is 800MHz. The core area (without I/O PAD) is 0.015 mm2 , There will be a simulation result at the last half of this thesis, which confirms the proposed circuit has improved certainly these drawbacks of SMD.
Appears in Collections:	[Executive Master of Electrical Engineering] Electronic Thesis & Dissertation

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