全數位式互補金屬氧化半導自我取樣延遲線電路用於時脈抖動量測; All Digital CMOS Self-sample Vernier Delay Line Circuit for Clock Jitter Measurement

NCU Institutional Repository > 資訊電機學院 > 電機工程研究所 > 博碩士論文 > Item 987654321/9952

請使用永久網址來引用或連結此文件: http://ir.lib.ncu.edu.tw/handle/987654321/9952

題名:	全數位式互補金屬氧化半導自我取樣延遲線電路用於時脈抖動量測;All Digital CMOS Self-sample Vernier Delay Line Circuit for Clock Jitter Measurement
作者:	黃展緯;Chan-Wei Huang
貢獻者:	電機工程研究所
關鍵詞:	尺規延遲線;自我取樣;抖動量測;jitter measurement;vernier delay line;self-sample
日期:	2006-07-06
上傳時間:	2009-09-22 12:01:46 (UTC+8)
出版者:	國立中央大學圖書館
摘要:	隨著半導體製程的進步，積體電路發展已朝向系統整合方式發展，當許多的系統整合在一個晶片中，各電路的時序的掌控必須是要很準確，要是產生時脈歪曲就可能造成電路動作錯誤。所以在系統中，時脈訊號關係整個電路的效能，而鎖相迴路電路就為一個重要時脈訊號建構單元。在鎖相迴路電路(PLL)中，輸出時脈抖動(jitter)的大小深深影響著鎖相迴路的效能，以往抖動的量測都是依靠著外部儀器來觀察其變化，但是，近年來，由於鎖相迴路操作頻率的一直提升，想要依靠外部儀器來量測抖動，必須要付出相當高的成本，來購買所需的儀器。加上外部儀器的雜訊，也會讓量測結果受到干擾。也因為上述這些原因，內建自我測試電路因而產生。利用內建量測電路來量測鎖相迴路的抖動，不僅可以減少測試成本，更可以加速抖動的量測，以及減少雜訊對量測結果的影響。以往的尺規延遲線電路，雖然可以產生出高解析度的電路，相對的會在電路硬體上消耗非常多，而此次設計的此次設計的全數位式互補金屬氧化半導體自我取樣尺規延遲線電路，則是採用兩階段的尺規延遲線，分別為one-period-delay circuit 跟jitter-measurement circuit，電路動作方式為首先利用One-period-delay circuit 快速延遲時脈到達需要量測的時間點，之後利用Jitter Measurement circuit製造出極高的解析度來量測抖動，如此一來，便可準確的量測鎖相迴路的抖動，又可以節省電路在硬體上的消耗。本次電路設計是使用TSMC 0.35um 2P4M的製程，one-period-delay circuit的電路解析度為300ps而jitter-measurement circuit的電路解析度為 15ps，電路所能量測的頻率範圍為100MHz~400MHz。 As the improvement of semiconductor technology, VLSI circuits has developed into System-On-a-Chip（SoC）. When many systems integrated into a chip, the sequence of clock of every circuit must be accurate. In the system, clock skew will affect the performance of the system. The Phase-Locked Loop (PLL) is recognized as one of the important components for clock recovery. In PLL circuits, the value of output clock jitter effect the performance of PLL. In the past, the jitter is measured by the external equipment. But, with the increased operating frequency, it will have a high cost on jitter measuring by external equipments. Sometimes probes of external equipments will be induced noise. The measurement result will be different. Because this reason, the built-in clock jitter measurement circuits are proposed. Using built-in clock jitter measurement circuits to measure the clock jitter that can reduce testing cost, decrease the effect of noise, and speeding up the jitter measurement. In the past, the vernier delay line circuit has high circuit resolution but high chip area. In this all digital CMOS self-sample vernier delay line circuit has two stages. One is one-period-delay circuit, the other is jitter measurement circuit. In this circuit, the one-period-delay circuit is used to delay the clock to measurement point quickly and the jitter measurement circuit created high circuit resolution to measure the jitter. In this way, the circuit can measure the clock jitter quickly and accurately and reduce the chip area. The proposed circuit is designed in TSMC 0.35um 2P4M CMOS process. The resolution of one-period-delay circuit is 300ps and that of jitter measurement circuit is 15ps. The measured frequency of the proposed circuit is 100MHz to 400MHz.
顯示於類別:	[電機工程研究所] 博碩士論文

文件中的檔案:

檔案	大小	格式	瀏覽次數

在NCUIR中所有的資料項目都受到原著作權保護.

社群 sharing

資料載入中.....