500MHz,30個相位輸出之鎖相迴路應用於三倍超取樣時脈回復系統; A 30phase 500MHz PLL for 3X Over-Sampling Clock Data Recovery

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Title:	500MHz,30個相位輸出之鎖相迴路應用於三倍超取樣時脈回復系統;A 30phase 500MHz PLL for 3X Over-Sampling Clock Data Recovery
Authors:	陳昭安;Chao-An Chen
Contributors:	電機工程研究所
Keywords:	時脈回復系統;三倍超取樣;鎖相迴路;clock data recovery;PLL;Over-Sampling
Date:	2006-06-22
Issue Date:	2009-09-22 12:01:51 (UTC+8)
Publisher:	國立中央大學圖書館
Abstract:	隨著製成技術的進步以及各個運算處理速度的提升，傳送接收系統應用在高速上是未來的趨勢，例如應用在乙太網路及光纖網路上的如10GBase-LX4、OC192、OC768等。而著重在有線或是匯流排上的應用則有USB2.0、IEEE1394、SERIAL-ATA等系統，在此系統當中所傳送的資料速度多為Gb/s的等級。在高速傳送上，會有更多的困難需要克服。例如雜訊的處理，時脈產生器產生高速時脈等等的問題。本論文試著採用三倍超取樣的技術應用在接收端的電路上，並試著符合到PCI-Express II的規格。本論文是將接收端的電路應用在5Gb/s的資料傳送系統上，達到一個高速5Gb/s串列資料，經由接收端電路，解回十組並列500Mb/s的資料。其中，鎖相迴路(PLL)作為系統上的時脈產生器，用來對於輸入的資料做取樣的動作。而系統當中所需要切割出微小的時脈延遲來調整鎖相迴路的參考時脈相位則採用Blender 的電壓切割方式，切割出15ps左右的延遲相位，以達到系統上所規定的頻寬。三倍超取樣的方式比起兩倍超取樣來說可以達到較小的靜態相位誤差，且比起四倍或五倍的方式複雜度不至於太大。在整體電路實現上，我們採用0.13-um製程，1.2-V的電源供應來實現我們接收端的電路。 With the progress in the CMOS process technologies and the operating speed of the processor, high speed links in the transmitter and receiver system is the trend of the future. For example, 10Gbase-LX4, OC192, OC768 are used in Gigabit Ethernet and Fiber Channel; USB2.0, IEEE1394 and SERIAL-ATA are used in wire or bus serial links. Most of the system operate at the data rate attain to the level of Gb/s. With the increased operation frequency, the difficulties in the system design are also increased. These difficulties include noise handling and the generation of the sampling clock at high frequency in receiver side, etc. The thesis adopts 3X over-sampling techniques in the receiver circuit and tries to meet the specification of PCI- Express II. The thesis design a receiver circuit which is used in the one serial in data with 5Gb/s and retime them to 10 500Mb/s parallel out data. PLL circuit is used as the clock generation and the output clock signals of PLL are used to sample the input data. The small phase delay circuit is implemented by Blender delay to make approximately 15ps delay and is used to tuning the phase of PLL’s reference clock. The need of small phase delay is because of the specification of CDR bandwidth. Adopting the 3X over-sampling is considered that 2X over-sampling system has larger static phase error and circuit in 4X or 5X is too complex. The receiver system in the thesis is implemented with a 0.13-um CMOS technology with a 1.2V supply power.
Appears in Collections:	[Graduate Institute of Electrical Engineering] Electronic Thesis & Dissertation

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