在系統晶片的時代，隨著電路設計複雜度的增加，模擬所花費的時間也隨著增加，為了快速驗證設計者的電路，尤其是在混合電路的模擬上，許多努力都致力於將電路提高到行為層級描寫，以加快此設計流程。過去這幾年來，當設計者在發展類比電路或是混合信號電路的時候，SPICE電路模擬器一直都是最基本的設計與驗証工具，但是隨著半導體技術的不斷發展、推出市場的快速要求下……等等，傳統的SPICE模擬器再也無法滿足先進電路的設計需求了。此論文裡，我們提出了一套利用Verilog-A硬體描述語言建立二階三角積分調變器電路的行為模組，並且利用由下而上的(bottom-up)的驗證方法，將電路的非理想因素萃取出來，並建立了一套標準的萃取參數流程，使得我們此二階∑Δ調變器的行為模組能更接近實際傳統的電晶體層級的模擬結果。最重要的，我們提出此回填參數的方法能適用於各種多變的二階∑Δ調變器電路，使它不受制於電路特性的限制。 With increasing complexity of circuit design in the SoC period, designers have to spend more time for circuit simulation. In order to simulate the mixed signal circuits rapidly, we are going to describe the circuits in behavioral level instead of circuit level. In the past years, SPICE is a basic simulator of design and verification when developing analog or mixed-signal circuits. However, with the advance of semiconductor technology and rapid time-to-market requirement, SPICE simulator can not satisfy the requirements of advanced circuit design any more. In this thesis, we propose a module of behavioral level using Verilog-A to describe the second order sigma-delta modulator. Meanwhile, we use a bottom-up verification method to extract its non-ideal effects. Then, we establish a standard parameter extraction flow to make the result of our behavioral model for the second order sigma-delta modulator can be more close to the actual simulation results of transistor level. Most importantly, our method, which is called back calibration, can be used in various second order sigma-delta modulators.
