隨著CMOS製程技術迅速地進步，電晶體的大小不斷地變小，一片晶圓上的電晶體數目多達幾十億個，使得電路設計的複雜度提升到SoC(System on Chip)的階層。在SoC的時代裡，電路設計的趨勢逐漸走向包含數位電路以及類比電路的混合電路設計，處理如此龐大的設計，驗證的問題變得非常的困難，模擬所花費的時間也隨著增加，為了快速驗證設計者的電路，許多努力都致力於將電路提高到行為層級描寫，以加快此設計流程。過去這幾年來，當設計者在發展類比電路或是混合信號電路的時候，SPICE電路模擬器一直都是最基本的設計與驗証工具，但是隨著半導體技術的不斷發展、推出市場的快速要求(time to market)…等等，傳統的SPICE模擬器再也無法滿足先進電路的設計需求了。 此論文裡，我們提出了一套利用Verilog-A硬體描述語言建立ΣΔDAC類比電路的行為模型，並且利用由下而上(bottom-up)的驗證方法，將電路的非理想因素萃取出來，並建立了一套標準的參數萃取流程，使得我們的行為模型更接近實際傳統的電晶體層級(transistor level)的模擬結果，達到快速模擬又不失精確度的目的。 With the process technology innovating rapidly, the device size is continuing to scale down. In SoC era, traditional design techniques must be modified to solve the integration problems with over million gate counts in a single chip. The major design challenge is the issue of co-simulation speed to verify a mixed-signal system. Integrating all blocks at layout-level and running the low-level post-layout simulation become almost infeasible for modern large designs. Moreover, such traditional simulator like SPICE requires too much simulation time such that it cannot meet the designer’s demand due to the pressure of time to market. Therefore, building a behavioral model is necessary so that we could get the simulation results very soon. In this thesis, we use hardware description language Verilog-A to build the behavioral models of ΣΔDAC and use them to estimate and handle these two integration issues. We present a bottom-up extraction flow to extract the characteristic parameters for ΣΔDAC behavioral models in a short time. Then, we adjust these parameters to consider the non-ideal effects such that the behavioral model could be much closer to the simulation results of SPICE.
