隨著數位電路工作頻率的提升，信號受到時序抖動以及時脈偏移的影響也越來越劇烈。本篇論文將以正反器串做為模型，並且利用統計分析的方法，來分析數位電路傳輸時受到時序抖動以及時脈偏移影響時的傳輸品質。應用分析的結果找到最佳的時序設定，供設計者參考以提昇電路工作的可靠性。 As the frequency of digital logic circuit rises up, the influence of jitter and skew on the signal is getting more serious. In this thesis we build a model based on a D flip-flop chain and use a statistical method to evaluate the transmission quality of digital logic circuit affected by jitter and skew. The best timing setting can be determined and provided to designers to improve the circuit reliability via this evaluation.
