鍺量子點嵌入二氧化矽/氮化矽/二氧化矽層之浮點電晶體研製

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姓名

曾柏皓(Po-Hao Tseng) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

鍺量子點嵌入二氧化矽/氮化矽/二氧化矽層之浮點電晶體研製
(Ge QD SONOS nonvolatile Floating-dot transistors)

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摘要(中)

本論文主要是將不同鍺莫爾濃度之多晶矽鍺沉積至氮化矽層上，再利用選擇性平面氧化多晶矽鍺的方法形成不同尺寸大小的鍺量子點，並控制氧化條件將鍺量子點嵌入至氮化矽層內，形成SONOS 記憶體與鍺量子點結合的混合式 (hybrid) 記憶體元件。藉由此混合式記憶體元件，我們預期將可增進傳統SONOS 記憶體之寫入與抹除效率、記憶體窗口以及資料保存能力等記憶體特性。此外，利用氮化矽材料分離的缺陷及浮點儲存層的特性，也可以抑制傳統浮閘記憶體的側向漏電流問題，進而降低穿隧介電層的厚度，增進元件的寫入與抹除速度以及元件耐用性。再者，此元件結構及製程不僅簡單，更與現在CMOS 的製程完全相容。

摘要(英)

In this thesis, we have fabricated hybrid memory cells incorporating Ge quantum dots(QDs) into silicon/oxide/ nitride/oxide/silicon (SONOS) for nonvolatile memory application.Ge QDs are generated by thermally oxidizing poly-Si1-xGex, and their size is tunable by Ge content in poly-Si1-xGex and thermal oxidation condition.
We expected the Ge QD SONOS hybrid memory cells provide better program /erase speed, memory window, and data retention than conventional SONOS. This is benefical from the fact that both Si3N4 and QDs are discrete trapping centers, suppressing the leakage concern in floating gate memory. Therefore, the tunneling oxide thickness and the read/write bias, respectively, can be scaled down to improve program/erase speed and endurance. The most importance of this work is that the process of Ge QD SONOS hybrid memory is not only simple, but also compatible to the prevailing CMOS technology.

關鍵字(中)

★ 記憶體

關鍵字(英)

★ memory

論文目次

目錄
中文摘要............................................ i
英文摘要............................................ ii
致謝.................................................iii
目錄.................................................iV
圖目錄...............................................V
表目錄...............................................Vi
第一章簡介與研究動機
1-1 前言........................................1
1-2 非揮發性記憶體演進及介紹....................2
1-2-1 浮閘記憶體元件...............................3
1-2-2 SONOS記憶體元件..............................5
1-2-3 浮點記憶體元件...............................6
1-3 研究動機....................................9
1-4 論文架構....................................10
第二章快閃記憶體操作原理及可靠度特性
2-1 前言...........................................16
2-2 浮點記憶體操作原理...........................16
2-3 載子穿隧機制.................................17
2-3-1 Direct tunneling 穿隧機制................17
2-3-2 Fowler-Nordheim穿隧機制..................18
2-3-3 Frekel-Poole 傳輸機制....................19
2-3-4 Hot carrier injection....................20
2-3 非揮發性記憶體基本可靠度特性..................21
2-3-1 資料保存能力............................22
2-3-2 元件耐用性..............................22
第三章元件製程開發及電晶體製作流程
3-1 鍺量子點的形成...............................28
3-2 鍺量子點於氮化矽中的特性開...................29
3-2-2 鍺量子點嵌入氮化矽實驗..................29
3-3 Ge QD SONOS電晶體製作流程....................32
3-3-1 閘堆疊層製作............................33
3-3-2 閘堆疊蝕刻方法與流程....................34
3-3-3 元件後段製程流程........................37
第四章元件量測與分析
4-1 前言..........................................56
4-2 電晶體特性量測................................56
4-3 記憶體特性量測分析............................58
4-3-1 載子儲存特性分析........................58
4-3-2 寫入速度與記憶體窗口....................59
4-3-3 抹除速度................................61
4-3-4 資料保存時間............................62
4-3-5 元件耐用性..............................64
4-4 結論.........................................67
第五章總結與未來展望................................85
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參考文獻

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指導教授

李佩雯(Pei-Wen Li)

審核日期

2010-7-14

推文