應用氮化矽/二氧化矽/氮化矽堆疊形成電致可調變穿隧能障之鍺量子點電晶體之研製

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：75

、訪客IP：3.135.192.215

姓名

王裕淵(Yu-yuan Wang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

應用氮化矽/二氧化矽/氮化矽堆疊形成電致可調變穿隧能障之鍺量子點電晶體之研製
(Fabrication and Characterization of Germanium Quantum Dots MOSFET with Electric-field Induced Tunable Tunnel Barriers in Si3N4/SiO2/Si3N4 Stack.)

相關論文

★ 高效能矽鍺互補型電晶體之研製	★ 高速低功率P型矽鍺金氧半電晶體之研究
★ 應變型矽鍺通道金氧半電晶體之研製	★ 金屬矽化物薄膜與矽/矽鍺界面反應之研究
★ 矽鍺異質源/汲極結構與pn二極體之研製	★ 矽鍺/矽異質接面動態啓始電壓金氧半電晶體之研製
★ 應用於單電子電晶體之矽/鍺量子點研製	★ 矽鍺/矽異質接面動態臨界電壓電晶體及矽鍺源/汲極結構之研製
★ 選擇性氧化複晶矽鍺形成鍺量子點的光特性與光二極體研製	★ 選擇性氧化複晶矽鍺形成鍺量子點及其在金氧半浮點電容之應用
★ 鍺量子點共振穿隧二極體與電晶體之關鍵製程模組開發與元件特性	★ 自對準矽奈米線金氧半場效電晶體之研製
★ 鍺浮點記憶體之研製	★ 利用選擇性氧化單晶矽鍺形成鍺量子點之物性及電性分析
★ 具有自我對準電極鍺量子點單電洞電晶體之製作與物理特性研究	★ 具有自我對準下閘電極鍺量子點單電洞電晶體之研製

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

本論文旨在探討利用兩種不同寬能隙的介電材料(氮化矽、二氧化矽)形成三層堆疊介電層以達到電致可調變穿隧能障之效，期望藉此可降低浮點電晶體的寫入與抹除之電壓，更可提升其寫入/抹除的效率。當閘極施予偏壓時，將使穿隧位能障產生近似對稱三角幾何的位能障來增加載子的寫入/抹除速度，並且利用低壓化學氣相沉積系統沉積複晶矽鍺並藉由濕氧化的方式形成鍺奈米晶粒的製程技術相結合實現出鍺浮點電晶體。本論文中是以氮化矽/二氧化矽/氮化矽堆疊所形成之穿隧介電層，其中的二氧化矽是在溫度為1050 oC 的環境下，以乾氧化氮化矽的方式所形成的。此製程方法能有效地控制穿隧介電層的等效氧化層厚度在5 nm 以下。且藉由不同寬能隙材料堆疊所形成對稱三角幾何的穿隧位能障，更能有效的降低元件的操作偏壓以及提升元件的操作速度與耐用性，又能保有元件的儲存能力。本實驗所製作而成的鍺浮點電晶體，寫入/抹除操作偏壓可降低至8 V 以及-6 V、操作速度分別可達到1 ms 以及70 μs，便可使得元件產生0.6 V 的記憶窗口。在儲存能力方面，儲存時間經過1E8 秒之後，儲存的電荷量尚保存原本的58 %。而在耐用性方面，元件的寫入/抹除操作次數可達到1E6 次以上。

摘要(英)

In this thesis, we explored two wide bandgap insulators, silicon-dioxide and silicon nitride, as a stacked dielectric for forming a tunable tunnel barrier under electric-field modulation. The so-formed tunnel dielectric behaves like a symmetric quasi-triangle potential barrier, which is expected to enhance the read and write speeds for memory application. In addition, we also incorporate germanium quantum dots (QDs) to replace the floating poly-Si gate, so that a high speed and good charge retention Ge QDs flash memory is demonstrated.
The stacked tunnel dielectric of Si3N4/SiO2/Si3N4 is produced by thermally oxidizing amorphous Si3N4 at 1050 oC and its equivalent oxide thickness (EOT) is less than 5 nm. The so-formed stacked tunnel dielectric behaves like a quasi-triangle potential barrier under E-field manipulation. Incorporating Ge QDs with the quasi-triangle tunnel barrier into the MOSFET structure, we realized a floating-dot nonvolatile memory cell transistor with the write/read voltages of +8 V and -6 V, write/read time of 1 ms and 70 μs at a threshold voltage shift (ΔVTH = 0.6 V). This Ge QDs transistor have good charge retention of 58 % after 1E8 s and excellent endurance after more than 1E6 read/write operations.

關鍵字(中)

★ 鍺浮點電晶體
★ 電致可調變穿隧能障
★ 非揮發性記憶體

關鍵字(英)

★ E-field induced tunable tunnel barriers
★ nonvolatile memory
★ Ge floating dot transistor

論文目次

目錄
中文摘要………………………………………………i
英文摘要………………………………………………ii
致謝……………………………………………………iii
目錄……………………………………………………iv
圖目錄…………………………………………………vii
表目錄…………………………………………………xiv
第一章序論……………………………………………1
1-1 研究背景……………………………………………1
1-2 浮點的種類…………………………………………6
1-3 高介電係數材料的應用……………………………8
1-4 研究動機……………………………………………8
1-5 研究目的與應用……………………………………11
第二章浮點記憶體之操作原理………………………21
2-1 前言…………………………………………………21
2-2 浮點記憶體之寫入與抹除原理……………………21
2-3 載子穿隧注入………………………………………21
2-3-1 直接穿隧機制……………………………………22
2-3-2 Fowler-Nordheim 注入機制………………………23
2-3-3 Frenkel-Poole 注入………………………………24
2-3-4 通道熱電子注入…………………………………25
2-4 元件穿隧機制討論…………………………………26
第三章鍺浮點電晶體之製程與開發…………………32
3-1 前言…………………………………………………32
3-2 鍺奈米晶粒製作方法………………………………32
3-3 複晶矽鍺沉積在不同材料的物理性質……………33
3-3-1 前言………………………………………………33
3-3-2 沉積複晶矽鍺薄膜之潛伏期……………………33
3-3-3 複晶矽鍺沉積在二氧化矽、非晶矽以及氮化矽
　上的物理性質……………………………………34
3-4 濕氧氧化沉積在氮化矽上的複晶矽鍺層…………36
3-5 利用乾氧氧化氮化矽形成二氧化矽………………38
3-6 鍺浮點電晶體的製作流程…………………………40
3-6-1 元件隔離層的製作………………………………40
3-6-2 閘堆疊的製作……………………………………41
3-6-3 基板重摻雜………………………………………43
3-6-4 金屬電極…………………………………………43
3-7 閘堆疊層的分裂條件………………………………44
第四章鍺浮點電晶體的電性量測與分析……………57
4-1 前言…………………………………………………57
4-2 電晶體基本電性量測………………………………58
4-3 磁滯現象量測………………………………………58
4-4 複晶矽浮閘與鍺浮點電晶體的記憶體特性量測…59
4-4-1 寫入/抹除電壓與速度量測………………………60
4-4-2 儲存時間量測……………………………………65
4-4-3 耐用性量測………………………………………68
4-5 複晶矽浮閘與鍺浮點電晶體的電性量測分析……71
第五章總結與未來展望………………………………103
參考文獻………………………………………………104

參考文獻

參考文獻
[1] Roberto Bez et al, “Introduction to Flash Memory,” Proc. IEEE ,vol. 91,No. 4, 2003.
[2] S. M. Sze, Kwok K. Ng, Physics of Semiconductor Device. p. 350-351.
[3] S. M. Sze, Kwok K. Ng, Physics of Semiconductor Device. p. 352-360.
[4] W. K. Shih, E. X. Wang, S. Jallepalli, F. Leon, C. M. Maziar, and A. F. Tasch, Jr., “Modeling gate leakage current in nMOS structure due to tunneling through an ultra-thin oxide,” Solid-State Electron., 42, 997(1998).
[5] Sandip Tiwari, “A silicon nanocrystals based memory,” Applied Physics Letters, vol. 68, p. 1377, 1996.
[6] J. Dufourcq et al, “High density platinum nanocrystals for non-volatile memory applications,” Applied Physics Letters, vol. 92, pp. 073102, 2008.
[7] J. J. Lee, Dim-Lee Kwong, “Metal nanocrystal memory with high-k tunneling barrier for improved data retention,” IEEE Transaction on Electron Devices, vol.52, pp.507-511, 2005.
[8] S. Maikap et al, “Physical and electrical characteristics of atomic layer deposited TiN nanocrystal memory capacitors,” Applied Physics Letters, vol. 91, pp. 043114, 2007.
[9] 楊露瑜， “應用氮化矽作為穿隧介電層之鍺量子點電晶體之研製”，碩士論文，國立中央大學，民國97年。
[10] Byoungjun Park et al., “Memory characteristics of Al nanocrystals embedded in Al2O3 layers,” Microelectronic Engineering, vol. 84, 2007, p. 1627-1630.
[11] X. Wang et al., “A novel high-k SONOS memory using TaN/Al2O3/Ta2O5/HfO2/Si structure for fast speed and long retention operation,” IEEE Transaction on Electron Devices, vol. 53, No.1, 2006.
[12] Konstantin K. Likharev, “Layered tunnel barriers for nonvolatile memory devices,” Applied Physics Letters, vol. 73, No. 15, 1998.
[13] Y. Liu et al, “Improved performance of SiGe nanocrystal memory with VARIOT tunnel barrier,” IEEE Trans. Electron. Device, vol. 53, No. 10, pp. 2598-2602, 2006.
[14] Julie D. Casperson et al, “Materials issues for layered tunnel barrier structure,” J. Appl. Phys., vol. 92, No. 1, pp.261-267, 2002.
[15] W. T. Lai and P. W. Li, “Growth kinetics and related physical/electrical properties of Ge quantum dots formed by thermal oxidation of Si1-xGex-on-insulator,” Nanotechnology, vol. 18, p. 145402, 2007.
[16] A. S. Grove, Physics and Technology of Semiconductor Devices. New York：Wiley, 1967.
[17] Yuan Taur, Tak H. Ning, Foundamentals of Modern VLSI Devices. p. 96.
[18] Y. Takahashi and K. Ohnishi, “Estimation of Insulation Layer Conductance in MNOS Structure,” IEEE Trans. Electron Dev., ED-40, 2006 (1993).
[19] J. H. Wu and P. W. Li, “Ge nanocrystals metal-oxide-semiconductor transistors with Ge nanocrystals formed by thermal oxidation of poly-Si0.88Ge0.12,” Semiconductor Science and Technology, vol. 22, p. S89, 2001.
[20] K. K. Ng and G. W. Taylor, “Effects of Hot-Carrier Trapping in n- and p-Channel MOSFET’s,” IEEE Trans. Electron Dev., ED-30, 871 (1983).
[21] Chuan-Hsi Liu and Jin-Lai Chen, Semiconductor Device Physics and Process：Theory & Practice. P.235.
[22] S. M. Sze, Kwok K. Ng, Physics of Semiconductor Device. p. 227-229.
[23] Zhung L, Gyo L and Chou S. Y., IEEE Int. Electron Devices Meeting, p. 167, 1997.
[24] Y. Maeda et al, “Visible photoluminescence of Ge microcrystals embedded in SiO2 glassy matrices,” Applied Physics Letters, vol. 59, p. 3168, 1991.
[25] K. V. Shcheglov, et al, “Electroluminescence and photoluminescence of Ge-implanted Si/SiO2/Si structures,” Applied Physics Letters, vol. 66, p. 745, 1995.
[26] Valentin Craciun et al, “Light emission from germanium nanoparticles formed by ultraviolet assisted oxidation of silicon-germanium,” Applied Physics Letters, vol. 69, p. 1506, 1996.
[27] P. W. Li et al, “Formation of atomic-scale germanium quantum dots by selective oxidation of SiGe/Si-on-insulator,” Applied Physics Letters, vol. 83, p. 4628, 2003.
[28] T. Kobayashi et al, “Ge nanocrystals in SiO2 films,” Applied Physics Letters, vol. 71, p. 1195, 1997.
[29] Tsu-Jae King and K. C. Saraswat, “Deposition and properties of low-pressure chemical-vapor deposited polycrystalline silicon-germanium films,” Journal of Electrochemical Society, vol. 141, No. 8, p. 2235, 1994.
[30] Min Cao, Albert Wang, Krishna C. Saraswat, “Low pressure chemical vapor deposition of Si1-XGeX film on SiO2,” Journal of Electrochemical Society, vol. 142, No. 5, p. 1566, 1995.
[31] S. S. Tzeng and P. W. Li, “Enhanced 400-600 nm photoresponsivity of metal-oxide-semiconductor diodes with multi-stack germanium quantum dots,” Nanotechnology, vol. 19, p. 235203, 2008.
[32] 徐紹華， “具有自我對準下閘電極鍺量子點單電洞電晶體之研製”，碩士論文，國立中央大學，民國96年。
[33] Honghua Du, Richard E. Tressler, and Karl E. Spear, “Thermodynamics of the Si-N-O system and kinetic modeling of oxidation of Si3N4,” Journal of Electrochemical Society, vol. 136, No. 11, p. 3210, 1989.
[34] 曾柏皓， “鍺量子點嵌入二氧化矽/氮化矽/二氧化矽層之浮點電晶體研製”，碩士論文，國立中央大學，民國99年。
[35] H. K. Liou, P. Mei, U. Gennser, and E. S. Yang, “Effects of Ge concentration on SiGe oxidation behavior,” Applied Physics Letters, vol. 59, p. 1200, 1991.
[36] 陳冠宏， “應用於高效率單電子元件鍺量子點之研製：鍺量子點定位與定量之探討”，碩士論文，國立中央大學，民國98年。
[37] 汪建民，Materials Analysis. p. 224-234.
[38] M. H. White et al, “On the go with SONOS,” IEEE Circuits Devices Mag., vol. 16, No. 4, pp. 22-31, Jul. 2000.
[39] 許書豪， “非揮發性鍺量子點掩埋於二氧化矽/氮化矽複合穿隧介電曾知MOS電容研製與載子傳輸機制之探討”，碩士論文，國立中央大學，民國97年。

指導教授

李佩雯(Pei-wen Li)

審核日期

2010-8-16

推文