擁有全信號觀察能力的嵌入式測試向量加速技術

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莊青龍(Chin-Lung Chuang) 查詢紙本館藏

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電機工程學系

論文名稱

擁有全信號觀察能力的嵌入式測試向量加速技術
(Embedded Testbench Acceleration with Full Signal Visibility for Functional Verification)

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摘要(中)

以現況來說，驗證仍然是IC設計流程中的主要瓶頸，當使用硬體輔助來加速模擬的方法以提升速度時，介於電腦主機與硬體加速器間額外產生的通信負擔，卻轉變成效能提升最大的障礙。此外，當設計放到硬體加速器之後，不良的信號觀察能力又是另一個除錯時令人頭痛的問題。因此，這篇論文將針對這兩個問題提出討論與解決方案。
在測試向量加速技術中，因為硬體和軟體分別放在不同的平台會造成額外的通訊負擔，使得舊有的方法不能兼顧效能與測試向量的相容性。因此，本論文提出了嵌入式測試向量加速技術，把原來會額外增加的通訊負擔降到最低，因此這個方法可以大幅的增加模擬的速度。本論文透過實際業界的例子加以實驗證明，我們的方法大約比業界的工具約快了十倍以上，不但如此，額外占用的硬體資源僅約百分之 0.57。由此可說明嵌入式測試向量加速技術是非常有效率的加速方式，卻又不需要占用太多昂貴的硬體資源。
另外，硬體原型平台在功能驗證中是極為重要的最後一個關卡，因為它擁有很高效率的運行速度，但是FPGA與生俱來的除錯能力卻非常之有限，因此，這篇論文提供另一個新穎的方法，即分段紀錄FPGA內部信號的狀態，並事後利用軟體模擬器撥放的方式，模擬出使用者想要觀察的區段信號。透過這個方法，我們仍然能夠擁有極高的運行速度，因為所有的運算已經由FPGA完成，而所有的信號仍然可以像軟體模擬器一樣被觀察到，大幅增加除錯的效率，最終也以實驗來驗證這個方法的優點。

摘要(英)

Nowadays, verification is still a primary bottleneck in the design flow. While using the simulation acceleration techniques to speed up the simulation-based verification, the communication overhead between the host machine and accelerator often appears as an extra overhead that limits the obtained improvement. In addition, after the designs are put into the hardware-based accelerators, the poor visibility of internal signal becomes another issue while tracing the possible bugs. Therefore, the focuses of this dissertation are put on those two primary issues.
Due to the communication overhead between hardware and software, traditional simulation acceleration has to compromise between testbench compatibility and performance. In this dissertation, a new approach, named as Hybrid Embedded Testbench Acceleration (HETA), is proposed to reduce this communication overhead. This method can avoid the communication issue and greatly improve the simulation speed. Experimental results on an industry case show that the proposed HETA approach is about 10 times faster than a commercial hardware accelerator with only 0.57% hardware overhead. This demonstrated that HETA is an efficient solution to further reduce the simulation time for functional verification with less overhead.
Hardware prototype is very important in last stage of functional verification, due to its high simulation speed. However, it is very hard to debug using this approach due to poor visibility in the FPGA. Therefore, in this dissertation, propose another approach to “record” the internal behaviors of a FPGA and “replay” the interesting period of time in a software simulator. In this way, we can still have high simulation speed because most simulation efforts are still finished in the FPGA. Besides, full visibility and better debugging environment can be provided in the software simulation. The experimental results have shown the efficiency of using our approach.

關鍵字(中)

★ 測試向量加速模擬除錯信號觀察功能驗證

關鍵字(英)

★ emulation
★ simulation acceleration
★ testbench
★ signal visibility
★ prototype
★ debug
★ scan chain
★ functional verification
★ FPGA

論文目次

Chapter 1 Introduction - 1 -
1.1 Verification Bottleneck - 1 -
1.2 Existing Verification Approaches - 7 -
1.3 Communication Overhead in Simulation Acceleration - 13 -
1.4 Signal Visibility in Hardware- Based Prototyping - 18 -
1.5 Key Contributions - 20 -
1.6 Dissertation Organization - 22 -
Chapter 2 Hybrid Embedded Testbench Acceleration - 24 -
2.1 Related Works - 24 -
2.2 HETA Mechanism - 28 -
2.3 Hardware Implementation - 33 -
2.3.1 Event Detector - 34 -
2.3.2 Time Wheel Scheduler (TWS) - 34 -
2.3.3 Behavioral Testbench Processing Unit (BTPU)- 35 -
2.3.4 Synthesizable Behavioral Logic (SBL) - 37 -
2.3.5 Concurrent Function-slices Execution Controller (CFEC) - 38 -
2.3.6 Interface Signal Registers (ISR) - 38 -
2.3.7 Clock Controller - 39 -
2.4 Experimental Results - 40 -
2.5 Summary - 42 -
Chapter 3 Hybrid Approach for Visibility Improvement - 43 -
3.1 Motivation - 43 -
3.2 Snapshot and Reconstruction Mechanisms - 47 -
3.2.1 Recording Internal Behavior in a FPGA - 47 -
3.2.2 Waveform Reconstruction - 49 -
3.2.3 FPGA Implementation - 50 -
3.2.4 Snapshot for Embedded Memory - 53 -
3.3 Storage Data Reduction - 54 -
3.3.1 Some Observation for Reducing Storage Data - 54 -
3.3.2 Design Modeling Using S-Graph - 57 -
3.3.3 Translation of Node Selection Problem - 57 -
3.3.4 Modified Snapshot Mechanism - 58 -
3.4 Experimental Results - 60 -
3.5 Summary - 66 -
Chapter 4 Conclusions and Future Works - 68 -
Reference - 70 -
Publication List - 75 -

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指導教授

劉建男(Chien-Nan Jimmy Liu)

審核日期

2011-1-4

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