K/V頻段低功率消耗低雜訊放大器暨K頻段混頻器之研究

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姓名

柯志霖(Zhi-lin Ke) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

K/V頻段低功率消耗低雜訊放大器暨K頻段混頻器之研究
(The Study on Low Power Consumption K/V Band Low Noise Amplifiers and K Band Mixer)

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摘要(中)

本論文內容為K/V頻段低功率消耗低雜訊放大器暨K頻段混頻器之研究。其中K頻段電路分別為低雜訊放大器與混頻器使用tsmcTM 0.18 μm製程。另外，V頻段電路為低雜訊放大器使用tsmcTM 90nm製程。
第一部分介紹K頻段放大器之實作，電路架構為三級共源級(C.S.)放大器，於第一級電路採用體偏壓(body bias)技術，藉此改變Vt以降低VDD，進一步減少功率消耗，因為級間少了耦合電容，其電壓亦後級的偏壓，故可以少一組PAD，以縮小電路佈局。量測上在25 GHz增益為11.15 dB，輸入與輸出反射係數分別為-6.1 dB及-7.6 dB，雜訊指數為5.12 dB，輸入三階交互調變交叉點為-7.5 dBm，電路功率消耗為4.9 mW，晶片面積為0.395 mm2。接著介紹V頻段低雜訊放大器之實作，電路架構使用電流再利用(current-reuse)的架構，可將兩級的共源極疊接，共用一路電流，進而節省功率及提高增益。在電晶體的尺寸與偏壓選取方面，先制定功率消耗，由電流密度反推一組合適的尺寸，並得電晶體最佳的fT、fmax、最大可允許增益(MAG)以及雜訊最小值(NFmin)。量測上在52 GHz增益為11.8 dB，輸入與輸出反射係數分別為-12 dB及-10 dB，雜訊指數為6.9 dB，輸入三階交互調變交叉點為-8 dBm，電路功率消耗為8.1 mW，晶片面積為0.378 mm2。
第二部分介紹K頻段混頻器之實作，RF與IF分別為24 GHz與10 MHz。本設計提出電流再利用技術應用在轉導級，成功地提升毫米波混頻器之轉換增益，以PMOS摺疊當作單平衡混頻開關級操作在23.99 GHz，達到低功率消耗且高轉換增益的設計目標。量測上在24 GHz轉換增益為15.1 dB，輸入三階交互調變交叉點為-6.7 dBm，三端的隔離度均小於-20 dB，電路功率消耗為4.06 mW，晶片面積為0.45 mm2。

摘要(英)

The content of this thesis is the research of low power consumption K/V band LNA and K band mixer. K-band LNA and mixer were implemented in tsmcTM 0.18 μm CMOS technology. V-band LNA was implemented in tsmcTM 90 nm CMOS technology.
　　The first section describes the design of K-band LNA. The LNA consists of three cascade common source amplifiers. The first stage adopts body-bias technique to change Vt which effectively reduces VDD and power consumption. The VDD is used to bias the next stage that saves a PAD. The arrangement can reduce the circuit area. The LNA achieves a measured peak power gain of 11.15 dB at 25 GHz. The input and output return losses are 6.1 dB and 7.6 dB, respectively. The measured NF is 5.12 dB and the measured IIP3 is -7.5 dBm. The power consumption is 4.9 mW. The chip area is 0.395 mm2. V-band LNA adopts the current reuse technique which is constructed by two stacked common source amplifiers. The current reuse topology shares the same supply current to reduce power consumption and improves the power gain. The transistor size and bias condition are firstly determined at fixed power consumption. The fT, fmax, maximum available gain (MAG) and NFmin of transistor are evaluated by different total width and current density. The V-band LNA achieves a measured peak power gain of 11.8 dB at 52 GHz. The input and output return losses are 12 dB and 10 dB respectively. The measured NF of the LNA is 6.9 dB and the measured IIP3 is -8 dBm. The power consumption is 8.1 mW. The chip area is 0.378 mm2.
The RF/IF frequencies of the differential K-band mixer are 24 GHz and 10 MHz, respectively. The current reuse technique is adopted in trans-conductance stage to enhance the conversion gain. The single balanced LO stage is formed by folded PMOS switch operating at 23.99 GHz that achieves the design goals of low power consumption and high conversion gain. The designed mixer achieves a conversion gain of 11.8 dB at 24 GHz. The measured IIP3 is -6.7 dBm. The port-to-port isolations are better than -20 dB. The power consumption is 4.06 mW. The chip area is 0.45 mm2.

關鍵字(中)

★ 混頻器
★ 低功率
★ 低雜訊放大器

關鍵字(英)

★ low noise amplifiers
★ mixer
★ low power consumption

論文目次

中文摘要 I
英文摘要 II
致謝 IV
目錄 VI
圖目錄 VIII
表目錄 XI
第一章緒論 1
1-1 研究動機 1
1-2 研究結果 2
1-3 章節簡述 2
第二章 K頻段與V頻段雜訊放大器之研製 3
2-1 簡介 3
2-2 低雜訊放大器之雜訊分析 4
2-3 低雜訊放大器之設計流程 6
2-3-1　低雜訊放大器之重要參數　　6
2-3-2　電路設計流程　　　　　　　10
2-4 K頻段低雜訊放大器之實作 12
2-4-1　電路架構　　12
2-4-2　模擬與量測結果　　　　　　17
2-4-3　結論　　　　　　　　　　　22
2-5　V頻段低雜訊放大器之實作 23
2-5-1　電路架構　　　　　　　　　23
2-5-2　模擬與量測結果　　　　　　28
2-5-3　結論　　　　　　　　　　　34
第三章 K頻段混頻器之研製 35
3-1　簡介　　　　　　　　　　　　35
3-2　混頻器之重要參數　　　　　　36
3-3　K頻段混頻器之實作　　　　40
3-3-1　電路架構　　　　　　　　　40
3-3-2　模擬與量測結果　　　　　　43
3-3-3　結論　　　　　　　　　　　49
第四章　結論　　　　　　　　　50
4-1　結論　　　　　　　　　　　　50
4-2　未來期許與展望　　　　　　　51
參考文獻　　　　　　　　　　　52

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指導教授

邱煥凱(Hwann-kaeo Chiou)

審核日期

2011-7-18

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