參考文獻 |
[1]林高伸,”奇普士的異想世界,” 國立交通大學, 2011年04月01日
[2]D. Long, Y. Zeng, C. Du, X. Hong, S. Dong, “A Novel Performance-Driven Automatic Layout Tool for Analog Circuit,” International Conference on Communications, Circuits and Systems, pp. 1344-1348, Jun. 2004.
[3]Z. Liu, L. Zhang,“A Performance-Constrained Template-Based Layout Retargeting Algorithm for Analog Integrated Circuits,” 15th Asia and South Pacific , Design Automation Conference (ASP-DAC), 2010
[4]G. Jerke, J. Lienig” Constraint-driven Design — The Next Step Towards Analog Design Automation,” International Symposium on Physical Design - ISPD , pp. 75-82, 2009
[5]Lihong Zhang, Ulrich Kleine, and Yingtao Jiang,” An Automated Design Tool for Analog Layouts,” IEEE transactions on very large scale integration (vlsi) systems, vol. 14, no. 8, august 2006
[6]J. M. Cohn, D. J. Garrod, R. A. Rutenbar, and L. R. Carley,“KOAN/ANAGRAM II: New tools for device-level analog placement androuting,” IEEE J. Solid-State Circuits, vol. 26, pp. 330-342, Mar. 1991.
[7]K. Lampaert, G. Gielen, and W. Sansen, “Analog Layout Generation for Performance and Manufacturability, “ Boston, MA: Kluwer, 1999.
[8]N. Jangkrajarng, S. Bhattacharya, R. Hartono, and C. Shi, “IPRAIL—Intellectual property reuse-based analog IC layout automation,” Integration. VLSI J., vol. 36, no. 4, pp. 237–262, Nov. 2003.
[9]林柏宏, “階層式類比電路之擺置,” 國立台灣大學電機資訊學院電子工程學博士論文, June. 2009.
[10]P.-H. Lin, S.-C. Lin, “Analog Placement Based on Hierarchical Module Clustering,” IEEE/ACM Design Automation Conference, pp. 50-55, Jun. 2008.
[11]Springsoft® Laker®,取自http://www.springsoft.com/ch/community/springsoft-foundation。
[12]黃弘一,”Ch03-Analog Layout Consideration,”混合訊號積體電路佈局與分析課程講義,Jan.2001.
[13]M. Eick, M. Strasser, H. Graeb, U. Schlichtmann,”Automatic Generation of Hierarchical Placement Rules for Analog Integrated Circuits,” ISPD’10, March 14–17, 2010
[14]L. Xiao, E.F.Y. Young, “ Analog Placement with Common Centroid and 1-D Symmetry Constraints,” Asia and South Pacific Design Automation Conference, pp. 353-360, Jan. 2009.
[15]S.Bhattacharya, N.Jangkrajarng, C.J.R. Shi,” Multilevel Symmetry-Constraint Generation for Retargeting Large Analog Layouts,” IEEE transactions on computer-aided design of integrated circuits and systems, vol. 25, no. 6, june 2006
[16]L. E. Han,”CMOS Transistor Layout KungFu,”2005
[17]黃弘一,”Ch06-Ch07,”混合訊號積體電路佈局與分析課程講義,Jan.2001.
[18]F. Balasa and K. Lampaert. ”Symmetry within the Sequence-Pair Representation in the Context of Placement for Analog Design,” IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems, 2000.
[19]Y-x. Pang, F. Balasa, K. Lampaert and C-K Cheng, “Block Placement with Symmetry Constraints based on the O-tree Nonslicing Representation. ,”Proceedings of the 37th ACMlIEEE Design Automation Coriference, pages 464-467, 2000
[20]F. Balasa, S.-C Maruvada and K.Krishnamoorthy, “On the Exploration of the Solution Space in Analog Placement with Symmetry Constraints,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 23(2): 177-191, 2004.
[21]J. Liu, S. Dong, Y. Ma, D. Long, X. Hong. “Thermal-driven Symmetry Constraint for Analog Layout with CBL epresentation.” IEEE Asia South Pacific Design Automation onference, pp. 191-196, 2007.
[22]Y-C Chang, Y-W Chang, G-M Wu, and S-W Wu. “B*-trees: A new representation for non-slicing floorplans.” In ACM/IEEE Design Automation Conference (DAC), volume 37, pages 458–463, 2000.
[23]Q. Ma, E. F. Y. Yong, and K. P. Pun. “Analog placement with ommon centroid constraints.” In IEEE/ACM nternational Conference on Computer-Aided Design (ICCAD), November 2007.
[24]L. Zhang anad C-J R Shi and Y Jiang. “Symmetry-Aware Placement ith Transitive Closure Graphs for Analog Layout Design.” IEEE Asia outh Pacific Design Automation Conference, 2008.
[25]Q. Ma, L. Xiao, Y.-C. Tam, and E. F. Y. Young “simultaneous Handling Of Symmetry, Common Centroid, And General Placement Constraints,” IEEE transactions on computer-aided design of integrated circuits and systems, vol. 30, no. 1, january 2011
[26]J-M Lin and Y-W Chang. “Tcg-s: Orthogonal coupling of padmissible representations for general floorplans.” IEEE Transactions on Computer-Aided Design of Circuits and Systems, 23(6):968–980, June 2004.
[27]P -H. Lin and R-C Lin, “ Analog Placement based on Novel Symmetry Island Formulation. “ Proceedings. Design Automation Conference, pp. 465-470, 2007.
[28]Y.-C. Tam, E.F. Y. Young, and C. Chu. “Analog placement with symmetry and other placement constraints.” In IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2006.
[29]R.C.-López, O.Guerra, E.Roca, and F.V.Fernández “An Integrated Layout-Synthesis Approach for Analog ICs “IEEE transactions on computer-aided design of integrated circuits and systems, vol. 27, no. 7, july 2008
[30]J.D. Conway ,G.G. Schrooten,” An Automatic Layout Generator for Analog Circuits,” Proc. [3rd] European Conference, Design Automation, 1992.
[31]劉深淵,”鎖相迴路,” 滄海出版社,2006.
[32]C. Flynt, M. Kaufmann “TCL/TK A Developer’s Guide,” May. 2003.
[33]Rick, “TCL Tutorial 基本語法與指令,” 2003
[34]高雄應用科技大學,IC Layout 教師研習營課程講義,2009
[35]2011年6月,取自F. Maloberti, “Layout of Analog CMOS IC,”
[36]2011年6月,取自CIC教育訓練手冊
[37]R. C. Prim, “Shortest Connecting Networks and Some Generalizations,” Bell System Technical Journal, Vol. 36, pp. 1389-1401, Nov.1957.
[38]The User Guidelines for Dummy OD/PO/Metal Pattern Generation Utility with Calibre in TSMC 0.18um Process, CIC-CIS-2007-MA24_P_v1.0
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