高功率CMOS微波開關電路設計

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姓名

王志華(Chih-hua Wang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

高功率CMOS微波開關電路設計
(Design of High Power CMOS Microwave Switch)

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摘要(中)

由於CMOS製程擁有低成本和高度積體化的優點，因此使數位、類比與射頻電路逐步往系統晶片架構整合發展。然而CMOS的材料及元件例如:低的載子遷移率、低的崩潰電壓和較多的寄生電容特性，使得高頻及高功率相關電路的特性不彰。其中微波開關電路設計受限於不理想的基板效應，而使得功率承受能力降低。為了改善此問題，在本論文中提供了基板偏壓的方法和來改善高功率微波開關特性，並比較不對稱形式(asymmetrical)及行進波式(traveling-wave)的微波開關應用。
本論文首先有一導論，主要介紹高功率開關電路的相關研究和發展。接下來會分別介紹三個高功率開關電路。第一個開關電路在發射端子電路中應用了基底開關技術，1.9 GHz操作時此開關電路的發射端可以得到 29 dB的高隔離度。第二個高功率開關電路利用基底接電晶體式的電阻同時將佈局上的寄生效應加入模擬中，最後我們量測到此電路發射端的功率承受能力在1.9 GHz操作下為 28 dBm。第三個高功率開關電路主要為在接收端電晶體的閘極加入並聯的電晶體和使用基底給負偏壓技術，來提高功率承受能力和隔離度，我們量測到此電路發射端的功率承受能力提昇至 34.2 dBm。
此外，呈現一個使用雙閘極電晶體的行進波開關電路，我們根據理論和模擬結果證明雙閘極電晶體可以增加開關電路的功率承受能力；此開關的操作頻率為 15 到 70 GHz，量測到此行進波開關電路的0.3-dB壓縮點功率承受能力為 22 dBm，模擬中預測1-dB壓縮點功率承受能力為 24 dBm。

摘要(英)

Since the circuit design based on CMOS technology achieves the advantages of low cost and high integration capability. The SoC (system-on-chip) research has being developed with integrating the digital, analog, and RF circuits.
However, the material/device characteristics such as low mobility, low breakdown voltage, and large parasitic capacitance always degrade circuit performance for high-frequency and high-power applications. The substrate effect also influences the large-signal characteristic in the microwave switch design, leading to an inferior power handling capability. In order to improve the problem, a method, body/substrate bias, has been proposed in this thesis. The method also was applied to the asymmetrical and the traveling-wave switches.
An introduction, illustrating the relative research and development of high power CMOS switch, is presented. Three high-power switch designs for 1.9 GHz operation are following. The first switch demonstrates an isolation of 29 dB in TX sub-circuit with using the body switch technique. A NMOS transistor used to be a resistor at body node is designed and simulated with a layout parasitic effect in the second high-power T/R switch design. The measured power handling capability of TX switch exhibits an input 1-dB compression point of 28 dBm. The third switch incorporates a shunt transistor to the gate of RX transistor and uses the body biasing technique with negative bias. The power handling capability can further be improved to 34.2 dBm at 1.9 GHz.
In addition, a traveling-wave switch using a dual-gate transistor is presented. The operating frequency is ranging from 15 to 70 GHz. Based on the theory and the simulation results, the power handling performance can be improved by using dual-gate NMOS transistor in the switch. The measured power handling capability of this traveling-wave switch is about 22 dBm, where it presents 0.3-dB power compression point. The 1-dB power compression point of 24 dBm was also predicted in the simulation.

關鍵字(中)

★ 高功率
★ 微波開關

關鍵字(英)

★ High power
★ RF switch

論文目次

摘要 I
Abstract II
致謝 III
目錄 IV
圖目錄 VI
表目錄 X
第一章導論 1
1.1研究動機 1
1.2 相關研究發展 2
1.3 微波開關的相關研究成果 3
1.4 章節簡述 5
第二章高功率1.9 GHZ CMOS微波開關電路 7
2.1 簡介 7
2.2 常見高功率微波開關架構 8
2.3 高功率量測系統架構 11
2.4高功率1.9 GHZ CMOS 微波開關電路設計 13
2.4.1應用基底開關技術高功率1.9 GHz CMOS微波開關電路 13
2.4.1.1 基底浮接技術 14
2.4.1.2 電路設計 17
2.4.1.3 量測結果 22
2.4.2 高功率 1.9 GHz CMOS微波開關電路 26
2.4.2.1 電晶體佈局模擬與比較 26
2.4.4.2 基底給予負偏壓技術及改良 29
2.4.4.3 基底開關技術及改良 31
2.4.4.4 電路設計 34
2.4.4.5 量測結果 40
2.4.3 高接收端隔離度高功率1.9 GHz CMOS微波開關電路 44
2.4.3.1 CMOS 元件模型改善 44
2.4.3.2 閘極端加並聯電晶體設計 51
2.4.3.3 電路設計 53
2.4.3.4 模擬與量測結果 54
2.5 結論 62
第三章寬頻15 ~ 70 GHZ CMOS微波開關設計 63
3.1 簡介 63
3.2 寬頻微波開關電路觀念介紹 63
3.3 雙閘極電晶體設計與原理 65
3.4 寬頻15 ~ 70 GHZ CMOS微波開關電路設計 69
3.4.1 電路設計 69
3.4.2 模擬與量測結果 71
3.5結論 74
第四章結論 76
參考文獻 77
附錄A 口試問題回答 80

參考文獻

[1] K. Y. Lin, T. Wen-Hua, C. Ping-Yu, C. Hong-Yeh, W. Huei, and W. Ruey-Beei, “Millimeter-wave MMIC passive HEMT switches using traveling-wave concept,” IEEE Transactions on Microwave Theory and Techniques, vol. 52, no.8, pp. 1798-1808, Aug. 2004.
[2] R. H. Caverly and K. J. Heissler, “On-state distortion in high electron mobility transistor microwave and RF switch control circuits,” IEEE Transactions on Microwave Theory and Techniques, vol. 48, no.1, pp. 98-103, Jun. 2000.
[3] K. Miyatbuji and D. Ueda, “A GaAs high power RF single-pole dual throw switch IC for digital-mobile communication system,” IEEE Journal of Solid-State Circuits, vol. 30, no.9, pp. 979-983, Sep. 1995.
[4] W. Jih-Hsin, H. Hsieh-Hung, and L. Liang-Hung, “A 5.2.GHz CMOS T/R Switch for Ultra-Low-Voltage Operations,” IEEE Transactions on Microwave Theory and Techniques, vol. 56, no.8, pp. 1774-1782, Aug. 2008.
[5] L. Tzung-Yin and L. Sunyoung, “Modeling of SOI FET for RF switch applications,” 2010 IEEE in Radio Frequency Integrated Circuits Symposium (RFIC), pp. 479-482, 2010.
[6] H. Feng-Jung and K. K. O, “Single-pole double-throw CMOS switches for 900-MHz and 2.4-GHz applications on p- silicon substrates,” IEEE Journal of Solid-State Circuits, vol. 39, no.1, pp. 35-41, Jun. 2004.
[7] H. Ishida, Y. Hirose, T. Murata, Y. Ikeda, T. Matsuno, K. Inoue, Y. Uemoto, T. Tanaka, T. Egawa, and D. Ueda, “A high-power RF switch IC using AlGaN/GaN HFETs with single-stage configuration,” IEEE Transactions on Electron Devices, vol. 52, no.8, pp. 1893-1899, Aug. 2005.
[8] M. Masuda, N. Ohbata, H. Ishiuchi, K. Onda, and R. Yamamoto, “High power heterojunction GaAs switch IC with P-1dB of more than 38 dBm for GSM application,” Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1998. Technical Digest 1998., 20th Annual, 1998, pp. 229-232.
[9] A. Minsik, K. Hyun-Woong, L. Chang-Ho, and J. Laskar, “A 1.8-GHz 33-dBm P0.1-dB CMOS T/R Switch Using Stacked FETs With Feed-Forward Capacitors in a Floated Well Structure,” IEEE Transactions on Microwave Theory and Techniques, vol. 57, no.11, pp. 2661-2670, Nov. 2009.
[10] Y. P. Zhang, L. Qiang, F. Wei, A. Chew Hoe, and L. He, “A Differential CMOS T/R Switch for Multistandard Applications,” IEEE Transactions on Circuits and Systems II: Express Briefs, , vol. 53, no.8, pp. 782.786, Aug. 2006.
[11] T. Dinc, S. Zihir, and Y. Gurbuz, “ CMOS SPDT T/R switch for X-band, on-chip radar applications ” Electronics Letters, vol. 46, no.20, pp. 1382.1384, Sep. 2010.
[12] L. Xue Jun and Z. Yue Ping, “ Flipping the CMOS Switch ” IEEE Microwave Magazine, , vol. 11, no.1, pp. 86-96, Feb. 2010.
[13] I. B. Kai Chang, Vijay Nair, RF and Microwave Circuit and Component Design for Wireless Systems: A John Wiley & Sons, INC.
[14] Y. Mei-Chao, T. Zuo-Min, L. Ren-Chieh, K. Y. Lin, C. Ying-Tang, and W. Huei, “ Design and analysis for a miniature CMOS SPDT switch using body-floating technique to improve power performance ” IEEE Transactions on Microwave Theory and Techniques, , vol. 54, no.1, pp. 31-39, Jun. 2006.
[15] W. Ruey-Lue, L. Chien-Hsuan, S. Yan-Kuin, T. Chih-Ho, and J. Ying-Zong, “The Layout Geometry Dependence of the Power Cells on Performances and Reliability,” IEEE Microwave and Wireless Components Letters, vol. 20, no.12, pp. 687-689, Dec. 2010.
[16] A. Minsik, K. Byung Sung, L. Chang-Ho, and J. Laskar, “A High Power CMOS Switch Using Substrate Body Switching in Multistack Structure,” IEEE Microwave and Wireless Components Letters, vol. 17, no.9, pp. 682.684, Sep. 2007.
[17] G. Jyh-Chyurn and L. Yi-Min, “A New Lossy Substrate Model for Accurate RF CMOS Noise Extraction and Simulation With Frequency and Bias Dependence,” IEEE Transactions on Microwave Theory and Techniques, vol. 54, no.11, pp. 3975-3985, Nov. 2006.
[18] A. Samavedam, A. Sadate, K. Mayaram, and T. S. Fiez, “A scalable substrate noise coupling model for design of mixed-signal IC's,” IEEE Journal of Solid-State Circuits, vol. 35, no.6, pp. 895-904, Jun. 2000.
[19] L. Tong, T. Ching-Han, E. Rosenbaum, and K. Sung-Mo, “Substrate modeling and lumped substrate resistance extraction for CMOS ESD/latchup circuit simulation,” Design Automation Conference, 1999. Proceedings. 36th, 1999, pp. 549-554.
[20] A. Minsik, L. Chang-Ho, K. Byung Sung, and J. Laskar, “A High-Power CMOS Switch Using A Novel Adaptive Voltage Swing Distribution Method in Multistack FETs,” IEEE Transactions on Microwave Theory and Techniques, vol. 56, no.4, pp. 849-858, Apr. 2008.
[21] X. Haifeng and K. O. Kenneth, “A 31.3-dBm Bulk CMOS T/R Switch Using Stacked Transistors With Sub-Design-Rule Channel Length in Floated p-Wells,” IEEE Journal of Solid-State Circuits, vol. 42, no.11, pp. 2528-2534, Nov. 2007.
[22] A. Minsik, L. Chang-Ho, K. Byung-Sung, and J. Laskar, “3W SPDT antenna switch design using standard 0.18 ?m CMOS process,” 2008 IEEE MTT-S International Microwave Symposium Digest, 2008, pp. 555-558.
[23] A. Minsik, L. Chang-Ho, and J. Laskar, “CMOS High Power SPDT Switch using Multigate Structure,” IEEE International Symposium on Circuits and Systems, 2007. ISCAS 2007. 2007, pp. 3283-3286.
[24] K. Hyun-Woong, A. Minsik, L. Ockgoo, L. Chang-Ho, and J. Laskar, “A high power CMOS differential T/R switch using multi-section impedance transformation technique,” IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2010, pp. 483-486.
[25] S. F. Chao, H. Wang, C. Y. Su, and J. G. J. Chern, “A 50 to 94 GHz CMOS SPDT Switch Using Traveling-Wave Concept,” IEEE Microwave and Wireless Components Letters, vol. 17, no. 2, pp. 130-132, Feb. 2007.
[26] L. Ruei-Bin, K. Jhe-Jia, and W. Huei, “A 60-110 GHz Transmission-Line Integrated SPDT Switch in 90 nm CMOS Technology,” IEEE Microwave and Wireless Components Letters, vol. 20, no. 2, pp. 85-87, Feb. 2010.
[27] Y. Mei-Chao, T. Zuo-Min, and W. Huei, “A miniature dc-to-50 GHz CMOS SPDT distributed switch,” Gallium Arsenide and Other Semiconductor Application Symposium, 2005. EGAAS 2005. European, 2005, pp. 665-668.
[28] L. Qiang and Y. P. Zhang, “CMOS T/R Switch Design: Towards Ultra-Wideband and Higher Frequency,” IEEE Journal of Solid-State Circuits, vol. 42, no. 3, pp. 563-570, Mar. 2007.
[29] M. Byung-Wook and G. M. Rebeiz, “Ka-Band Low-Loss and High-Isolation 0.13 ?m CMOS SPST/SPDT Switches Using High Substrate Resistance,” IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2007, pp. 569-572.
[30] L. Zhenbiao and K. K. O, “15-GHz fully integrated nMOS switches in a 0.13-?m CMOS process,” IEEE Journal of Solid-State Circuits, vol. 40, no. 11, pp. 2323-2328, 2005.
[31] Y. A. Atesal, B. Cetinoneri, and G. M. Rebeiz, “Low-loss 0.13-?m CMOS 50 - 70 GHz SPDT and SP4T switches,” IEEE Radio Frequency Integrated Circuits Symposium, 2009., pp. 43-46.
[32] E. Adabi and A. M. Niknejad, “A mm-wave transformer based transmit/receive switch in 90nm CMOS technology,” Microwave Conference, EuMC 2009. European, 2009. pp. 389-392.

指導教授

辛裕明(Yue-Ming Hsin)

審核日期

2011-8-11

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