參考文獻 |
[1] W. T. Nye, E. Polak and A. Sangiovanni-Vincentelli, “DELIGHT: An optimization-based computer-aided design system,” IEEE International Symposium on Circuits and Systems, 1981, pp. 851-855.
[2] M. Hershenson, S. P. Boyd and T. H. Lee, “Automated design of folded-cascode op-amps with sensitivity analysis,” IEEE International Conference on Electronics, Circuits and Systems, vol.1, 1998, pp.121-124.
[3] L. Dai and R. Harjani, “CMOS switched-op-amp-based sample-and-hold circuit,” IEEE J. Solid-State Circuit, vol.35, no.1, 2000, pp. 109-113.
[4] G. Espinosa-Flores-Verdad and R. Salinas-Cruz. “Symmetrically compensated fully differential folded-cascode OTA,” Electronic Letters. vol. 35, no. 19, 1999, pp. 1603-1604.
[5] M. Kayal, ”Transistor-Level Analog IC Design,” Short Course Lecture Note, EPFL, Lausanne, Switzerland, 2004.
[6] R. Hägglund, E. Hjalmarson, and L. Wanhammar, “Automatic DeviceSizing in Analog Circuit Design,” National Conf. Radio Science(RVK), 2002, pp. 187-191.
[7] R. Hägglund, E. Hjalmarson, and L. Wanhammar, “Optimization-Based Device Sizing in Analog Circuit Design,” Swedish System-on-Chip Conference, Falkenberg, Sweden, 2002.
[8] E. Hjalmarson, R. Hägglund, and L. Wanhammar, “An Optimization-Based Approach for Analog Circuit Design,” European Conference on Circuit Theory Design, 2003, pp. 369-372.
[9] E. Hjalmarson, R. Hägglund, and L. Wanhammar, “A Design Platform for Computer-Aided Design of Analog Amplifiers,” Swedish System-on-Chip Conf., Eskilstuna, Sweden, 2003.
[10] R. Hägglund, E. Hjalmarson, and L. Wanhammar, “A Design Path for Optimization-Based Analog Circuit Design,” IEEE Midwest Symp. Circuits Syst. , 2002, pp. 287-290.
[11] F. El-Turky and E.E. Perry, BLADES: an arrificial intelligence approach to analog circuit design",IEEE Trans. on CAD, Vol. 8, No. 6,1989, pp. 680-692.
[12] J. Mahattanakul, J. Chutichatuporn, “Design Procedure for Two-Stage CMOS Opamp With Flexible Noise-Power Balancing Scheme,” IEEE Trans Circuits and Systems, vol. 52, no 8, 2005, pp. 1508–1514.
[13] C.-W. Lin, P.-D. Sue, Y.-T. Shyu, S.-J Chang, “A Bias-Driven Approach for Automated Design of Operational Amplifiers,” IEEE VLSI Design Automation and Test, 2009, pp. 118-121.
[14] Y.-T. Shyu, C.-W. Lin, Jin-Fu Lin and Soon-Jyh Chang, “A gm/ID-based synthesis tool for pipelined analog to digital converters,” IEEE VLSI Design Automation and Test, 2009, pp 299-30.
[15] P. Mandal, V. Visvanathan, “CMOS Op-Amp Sizing Using a Geometric Programming Formulation,” IEEE Transactions on Computer-Aided Design, vol. 20, no. 1, 2001, pp. 22-38.
[16] M.delM. Hershenson, S.P. Boyd, T.H. Lee, “Optimal design of a CMOS op-amp via geometric programming,” IEEE/ACM International Conference on Computer-Aided Design, vol. 20, no. 1, 2001, pp. 1-21.
[17] M. S. Bazarar, H. D. Sherali, and C. M. Shetty, “Nonlinear Programming,” Wiley, 1993, 2nd ed.
[18] F. Silveira, D. Flandre, P.G.A. Jespers, ” A gm/ID based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA,” IEEE J. Solid-State, vol. 31, no. 9, 1996, pp. 1314-1319.
[19] B. Razavi, “Design of analog CMOS integrated circuits”, McGraw-Hill Higher Education, 2001
[20] W. Gao, R. Hornsey, “A power optimization method for CMOS op-amps using sub-space based geometric programming,” IEEE Design Automation and Test in Europe, 2010, pp. 508-513.
[21] http://www.lindo.com/index.php?option=com_content&view=article&id=28&Itemid=4
[22] M. Loulou, S. Ait Ali, M. Fakhfakh, N. Masmoudi, “An optimized methodology to design CMOS operational amplifier,” IEEE International Conference on Microelectronics, 2002, pp. 14-17.
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