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姓名 林筠菁(Yun-Jing Lin) 查詢紙本館藏 畢業系所 電機工程學系 論文名稱 泛用型電路介面行為模型產生器及其圖形化使用者介面
(A Generic Behavior Model Generator for Interface Circuits with Graphical User Interface)相關論文 檔案 [Endnote RIS 格式]
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摘要(中) 隨著製程演進以及電路應用層面日趨廣泛，積體電路的設計複雜度日漸增高，所需的電路模擬驗證時間也大幅增加，連帶拖慢了整個設計流程完成的時間，尤其是在類比及數位電路之整合模擬(co-simulation)方面，仍舊有許多難以克服的因素，使得混合訊號設計的整合模擬目前仍有一定的困難度。以行為模型(behavior model)取代原始類比電路設計區塊，將模擬的層級提高，也是一個縮短模擬時間的方法。準確地建立行為模型後，能夠將行為模型與數位電路區塊整合模擬，檢驗類比與數位電路設計區塊之間訊號傳輸，以及電路反應行為是否正確並且符合預期。現今已存在的行為模型產生器(behavioral model generator)，大多是針對特定的電路，例如：專用於類比數位轉換器電路(analog to digital converter, ADC)抑或是鎖相迴路電路(Phase-locked loops, PLL)電路，難以廣泛運用於各種不同的系統中。
本論文對行為模型建立做研究，旨在以整合已存在之電路模型區塊的方法，提升行為模型產生器的泛用程度，依據電路模型區塊資訊以及區塊間訊號傳遞關係，整合各電路區塊自動產生相對應之電路介面行為模型(circuit interface behavioral model)，產出之行為模型可供後續應用於電路驗證程序；另外也提供圖形化介面協助使用者以更簡易的方式，指定訊號傳遞關係產生電路介面行為模型。摘要(英) With the development of the semiconductor technology, more and more applications of the integrated circuits are enabled with increasing complexity. Because many devices and building blocks are included in one integrated circuit, the simulation time of the design is significantly increased, which is the main difficulty that slows down the design procedure. For mixed-signal designs, there are still many difficulties to be solved for fast co-simulation. Replacing the original analog circuit block by corresponding behavior model is a solution for speeding up the simulation. If the behavior model is built accurately, the simulation level could be raised from transistor level to behavior level that enables the co-simulation with the digital part to check the signal interactions between analog and digital parts and the expected behavior of the entire system. Previous behavior model generators are often dedicated on particular circuit structures, such as ADC and PLL. It is not easy to extend those behavior model generators for different systems.
In this thesis, the target is to develop a generic behavior model generator that can integrate the existed behavior models in all design hierarchies. According to the user-provided information of the circuit blocks and the connections between then, the generator will automatically generate the hierarchical behavior model of this system incorporating the interface between circuit blocks. The generated behavior models can be applied to the following verification process. In addition, an easy-to-use graphical user interface is also provided in this work to help users specify the signal relationship of the interface model.關鍵字(中) ★ 行為模型
★ 產生器關鍵字(英) 論文目次 摘要 i
Abstract ii
目錄 iv
圖目錄 vi
表目錄 ix
第一章、緒論 1
1-1 研究動機 1
1-2 相關研究 6
1-3 論文結構 8
第二章、背景知識 9
2-1 電路行為模型簡介 9
2-2 斷言(Assertion)簡介 14
2-3 圖形化介面(Graphical User Interface)簡介 17
2-3-1 圖形化介面發展工具簡介 17
2-3-2 Qt 部件工具(Qt classes)簡介 19
第三章、階層式介面模型建構方法與流程 27
3-1 階層式建構電路介面模型 27
3-1-1 電路介面模型建構方法 27
3-1-2 電路介面模型建構方法 29
3-2 連結模組建構方法 30
3-2-1 連結模組內部架構 30
3-2-2 連結模組與電路區塊模組訊號傳遞實現方法 31
3-2-3 連結模組內部排序問題 33
3-3 電路介面行為模型之斷言產生 35
第四章、以圖形化介面輔助介面模型產生 37
4-1 主要功能介面流程與介紹 37
4-2 介面資訊及電路區塊模組之匯入與設定 40
4-2-1 資訊與模組匯入操作 40
4-2-2 電路區塊模組之元件(instance)設定 43
4-2-3 訊號指定操作介紹 44
4-3 指定連結操作步驟介紹 46
4-3-1 相等連結(Equivalent) 46
4-3-2 多工器(Multiplexer) 47
4-3-3 數學運算(Mathematic) 49
4-3-4 斷言指定(Assertion) 51
4-4同時指定相似元件之連結操作 53
4-5 連結指定之防護機制 54
第五章、結論與未來研究方向 57
第六章、參考文獻 58參考文獻 [1]M. J. Pennell, M. Hasan, D. R. Allee, W. Xie, “Behavioral Model of a 1.8V 6b CMOS Flash ADC Based on Device Parameters,” International Symposium on Circuits and Systems, vol. 3, pp. 1636-1639, 1997.
[2]J. Mentzer, T. Wey, “A Verilog Mixed Signal Model of a 10-bit Pipeline Analog-to-Digital Converter,” Behavioral Modeling and Simulation Workshop, pp. 115-119, 2006.
[3]C. B. Kim, “Automatic Behavioral Verilog Model Generation using Engineering Parameters”, International Verilog HDL Conference, pp. 108-114, 1994.
[4]R. Passerone, J.A. Rowson, and A. Sangiovanni-Vincentelli,“Automatic synthesis of interfaces between incompatible protocols,” Design Automatic Conference, pp. 8-13, 1998.
[5]Y.-T. Hwang, H.-H. Luo, “Automatic IP Interface Synthesis Supporting Multi-Layer Communication Protocols in SoC Designs,” Information Assurance and Security, vol 1, pp. 169-172, 2009.
[6]C. Borchers, L. Hedrich, E. Barke, “Equation-based behavioral model generation for nonlinear analog circuits,” Design Automation Conference Proceedings, pp. 236-239, 1996
[7]L. Nathke, V. Burkhay, L. Hedrich, E. Barke, “Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits Based on Nonlinear Symbolic Techniques,” Design, Automation and Test in Europe Conference and Exhibition, vol 1, pp. 442-447, 2004.
[8]“OpenVera Language Reference Manual:Assertions,” Synopsys, Inc., 2004
[9]“Property Specification Language Reference Manual,” Accellera, 2004
[10]B. Cohen,S. Venkataramanan and A. Kumari, “SystemVerilog Assertions Handbook,” VhdlCohen Publishing, 2010
[11]H. Foster, K. Larsen and M. Turpin, “Introduction to the New Accellera Open Verification Library,” Accellera Systems Initiative, 2006
[12]M. Siwinsk, “Incisive Assertion Library: Jump-Start Assertion-Based coverage-Driven Verification,” Cadence Design Systems, Inc., 2006
[13]J. K. Ousterhout, “Tcl and the Tk Toolkit,” Addison-Wesley Publishing Company, Inc., 1993
[14]Y.-C. Liao, Y.-L. Chen, X.-T. C., C.-N. Jimmy Liu, T.-C. Chen, “LASER–Layout-aware Analog Synthesis Environment on Laker,” Great Lakes Symposium on VLSI, pp. 107-112, 2013
[15]“Cadence User Interface SKILL Functions Reference,” Cadence Design Systems, Inc., 2002
[16]“SKILL Language User Guide,” Cadence Design Systems, Inc., 2003
[17]J. Blanchette and M. Summerfield, “C++ GUI Programming with Qt 4,” Prentice Hall, 2008指導教授 劉建男(Chien-Nan Liu) 審核日期 2013-7-30 推文 plurk
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