應用傳輸線型變壓器於X/K–Ka/V頻段全積體整合之寬頻互補式金氧半導體功率放大器研製

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：145

、訪客IP：3.147.55.155

姓名

郭晉瑋(Chin-Wei Kuo) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

應用傳輸線型變壓器於X/K–Ka/V頻段全積體整合之寬頻互補式金氧半導體功率放大器研製
(Implementation on Fully Integrated Wideband CMOS Power Amplifiers Using Transmission-Line Transformer for X/K–Ka/V-band Applications)

相關論文

★ 應用於筆記型電腦數位電視單極天線之研製	★ 應用於數位機上盒與纜線數據機之電纜多媒體傳輸標準多工濾波器
★ 印刷共面波導饋入式多頻帶與超寬頻天線設計	★ 微波存取全球互通頻段前向匯入式功率放大器與高效率Class F類功率放大器暨壓控振盪器電路之研製
★ 應用於矽基功率放大器與混頻器之傳輸線型變壓器研究	★ 應用於V-頻段射頻收發機前端電路之低功耗源極注入式混頻器之研製
★ 應用積體電路上方後製程與整合被動元件於互補式金氧半導體製程之系統封裝研究	★ 應用fT-倍頻電路架構於毫米波壓控振盪器與注入鎖定除頻器之研製
★ 應用於K / V 頻段低功耗混頻器之研製	★ 應用於K/V頻段之低功耗CMOS低雜訊放大器之研究
★ 應用於5-GHz CMOS射頻前端電路之低電壓自偏壓式混頻器與高線性化功率放大器之研製	★ 應用於 K 頻段射頻接收機之寬頻低功耗 CMOS 低雜訊放大器之研製
★ 應用磁耦合變壓器於K頻段之低功耗互補式金氧半導體壓控振盪器研製	★ 應用於K頻段之單向化全積體整合功率放大器與應用於V頻段之寬頻功率放大器研製
★ 應用於C/X頻段全積體整合之互補式金氧半導體寬頻低功耗降頻器與寬頻功率混頻器之研製	★ 應用於 5-11 GHz寬頻低雜訊放大器與5 GHz/11 GHz雙頻低雜訊放大器之研製

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

至系統瀏覽論文 ( 永不開放)

摘要(中)

本論文利用tsmcTM提供的0.18-μm CMOS 與90-nm CMOS製程，實現操作於毫米波頻段之寬頻功率放大器以及K頻段小型發射機。內文在設計上分成兩部份，第一部份為應用傳輸線型變壓器於全積體整合寬頻CMOS功率放大器之研究，為解決CMOS製程在設計寬頻功率放大器時所遇到之瓶頸，如基板損耗過大、轉導能力不佳與電晶體崩潰電壓過低等問題，分別在X頻段、K至Ka頻段與V頻段設計三個功率放大器，利用傳輸線型變壓器的低損耗及寬頻特性，改善放大器操作於毫米波頻段時之性能。此外，因應不同的頻段需求，第一顆晶片搭配線性化與功率結合技術改善放大器的線性度與提升輸出功率；第二顆晶片則結合達靈頓對與疊接架構，同時提升fT與電晶體轉導能力，使得用低階製程也能在毫米波頻段下獲得足夠的增益；第三顆晶片則是採用改良過之達靈頓架構，利用電流再利用技術使消耗電流減少，同時提升放大器之增益平坦度。第二部分則是利用0.18-μm CMOS製程設計一個可應用於K頻段調頻連續波技術的小型發射機，完成整個發射機系統的設計驗證。各電路量測之特性如下：
X頻段寬頻功率放大器，在未開啟預失真電路時，增益量測結果為24.4 dB，飽和輸出功率為21 dBm，1-dB增益壓縮點之輸出功率為18.6 dBm，功率增進效率（PAE）為9.9%，3-dB頻寬為6.4 GHz（6.5 GHz至12.9 GHz）；開啟預失真電路之後，其增益量測結果為 23.2 dB，飽和輸出功率提升至22 dBm，1-dB增益壓縮點輸出功率提升至20.8 dBm，功率增進效率為20.1%，3-dB頻寬為5.8 GHz（6.6 GHz至12.4 GHz）。此功率放大器在整個X頻段的範圍（8 GHz至12.4 GHz）之內，飽和輸出功率與功率增進效率分別大於21.3 dBm以及16.2%，晶片面積包含測試墊片為1.05 mm2。
K至Ka頻段達靈頓寬頻功率放大器，小訊號增益在17.8 GHz至34.6 GHz的頻段範圍內，量測結果為15.2 1 dB，同時具備不錯的增益平坦度。在26 GHz所量測之飽和輸出功率為19.5 dBm，1-dB增益壓縮點輸出功率為16 dBm，功率增進效率為10.2%，功率3-dB頻寬為15 GHz（18 GHz至33 GHz），對應的功率比例頻寬為58.8%，晶片面積包含測試墊片為0.86 mm2。
V頻段電流再利用達靈頓寬頻功率放大器，利用改良式的達靈頓架構與傳輸線型變壓器達到超寬頻的特性。其小訊號增益為16.4 dB，3-dB頻寬為26 GHz（33.3 GHz至59.3 GHz），對應的增益比例頻寬為56.2%，同時在40 GHz至55 GHz的頻段內具備不錯的增益平坦度。於35 GHz至60 GHz的頻段內，飽和輸出功率為9.9 ± 0.6 dBm，1-dB增益壓縮點輸出功率為4.7 ± 0.6 dBm，功率增進效率最高值為4.8%，晶片面積包含測試墊片為0.82 mm2。
應用於K頻段之小型發射機，電路經由12 GHz壓控振盪器產生訊號之後，由倍頻器將頻率提升至K頻段，最後經由小型功率放大器把訊號推送出去。其頻率可調範圍為22.8 GHz至24.5 GHz，可調頻寬為1700 MHz，同時在此範圍內之輸出功率達14.4 0.8 dBm，對應的功率增進效率為9%至14%之間。在控制電壓為1 V，偏移中心頻率1 MHz時之相位雜訊為-99.1 dBc/Hz，整體晶片面積包含測試墊片為0.76 mm2。

摘要(英)

A CMOS power amplifier (PA) with wideband, high output power and high efficiency is the most challenging circuit due to low-Q passive component, lossy substrate, low breakdown voltage and low maximum available gain (MAG) of the transistors, especially in millimeter-wave frequency. Therefore, broadband and low-loss impedance transformers are attractive especially in CMOS PAs. The contents of this thesis are divided into five parts. Chapter 1 gives the motivation of system applications. Chapter 2 introduces the basic theory and some design parameters of power amplifier. Chapter 3 presents several fully-integrated wideband PAs were fabricated in tsmcTM 0.18-μm and 90-nm CMOS technologies. The focus of this chapter is the research of transmission-line transformers (TLTs). TLTs can be exploited to perform broadband and low-loss impedance transformation. Therefore, three wideband PAs were designed by utilizing broadband and low-loss Guanella-type TLT as the matching networks with different frequency bands.
A full X-band PA with an integrated Guanella-type transformer and a pre-distortion linearizer in 0.18-µm CMOS was implemented in the first design. The broadband performance was achieved by using transformers including a differential Guanella-type TLT (DTLT) and two magnetically coupled transformers. The linearity of PA is enhanced by feedback topology and the use of pre-distortion linearizer. Over full X-band from 8 GHz to 12 GHz, the saturated output power (Psat) and the maximum power added efficiency (PAEmax) are higher than 21.3 dBm and 16.19%, respectively. The performances of output 1-dB gain compression point (OP1dB) and PAEP1dB are significantly improved by an output power of 2.2 dBm and a PAE of 12.1%, which contributes to power back-off operation for the application of linear modulation. The chip area, including pads, is 1.05 mm2.
In the second design, an 18 to 33 GHz fully-integrated Darlington PA with DTLTs demonstrated the wideband and high power performance compared with other Ka-band CMOS PAs. The Darlington cell with cascode topology was adopted as the power cell to elevate the MAG of the transistors in standard 0.18-μm CMOS technology for being capable of operating at Ka band. Moreover, utilizing broadband and low-loss DTLTs as the matching networks, the proposed PA exhibits a flat gain of 15.2±1 dB from 17.8 to 34.6 GHz. The 3-dB power bandwidth is from 18 to 33 GHz with the saturated output power of 19.5 dBm. The OP1dB of 16 dBm and PAE of 10.2% are achieved at 26 GHz under a power consumption of 711 mW. The chip size is 0.86 mm2 including test pads.
In the third disign, a wideband Darlington power amplifier using DTLTs and current-reused technique was fabricated in 90-nm CMOS technology for V-Band applications. Compare to the original Darlington topology, the proposed current-reused Darlington topology achieve the same gain-extension ability while consumes less current than that of conventional one. This wideband PA exhibits a peak gain of 16.4 dB, and 3-dB bandwidths from 33.3 to 59.3 GHz. The measured result shows the saturated power of 9.9 ± 0.6 dBm from 35 to 60 GHz. The OP1dB of 5.3 dBm and PAE of 4.8% are achieved at 50 GHz.
Chpater 4 develops a compact-size transmitter front-end for 24-GHz Frequency- Modulated Continuous-Wave (FMCW) applications, which is composed of voltage-controlled oscillator (VCO), frequency doubler and medium power amplifier. The measured oscillation central frequency is 23.7 GHz with the tunable frequency range from 22.8 to 24.5 GHz. The phase noise is -99.1 dBc/Hz at 1-MHz offset, and the maximum output power is 15.3 dBm. The total power consumption is 225 mW.
Finally, the conclusion and future work are given in Chapter 5.

關鍵字(中)

★ 功率放大器
★ 傳輸線型變壓器
★ 達靈頓架構
★ 磁耦合變壓器
★ 發射機
★ 毫米波電路

關鍵字(英)

★ power amplifier
★ transmission-line transformer
★ Darlington topology
★ transformer
★ transmitter
★ millimeter-wave circuit

論文目次

摘要 I
ABSTRACT III
誌謝 V
目錄 VII
圖目錄 IX
表目錄 XV
第一章緒論 1
1-1 研究動機 1
1-2 研究成果 2
1-3 章節簡介 2
第二章功率放大器 3
2-1 功率放大器簡介 3
2-2 功率放大器分類 5
2-3 功率放大器之參數定義 7
2-4 功率放大器之非線性效應 9
第三章應用傳輸線型變壓器之寬頻功率放大器研製 13
3-1 磁耦合變壓器與傳輸線型變壓器 13
3-1-1 磁耦合變壓器簡介 14
3-1-2 傳輸線型變壓器簡介 18
3-2 應用預失真技術與功率結合變壓器之X頻段寬頻功率放大器研製 27
3-2-1 研究現況 27
3-2-2 線性化與預失真技術簡介 29
3-2-3 應用預失真技術與功率結合變壓器之X頻段寬頻功率放大器設計 33
3-2-4 電路模擬與量測結果 45
3-2-5 結果比較與討論 55
3-3 應用傳輸線型變壓器之K–KA頻段達靈頓寬頻功率放大器研製 58
3-3-1 研究現況 58
3-3-2 達靈頓對電晶體分析 62
3-3-3 應用傳輸線型變壓器之K–Ka頻段達靈頓寬頻功率放大器設計 70
3-3-4 電路模擬與量測結果 76
3-3-5 結果比較與討論 83
3-4 應用傳輸線型變壓器之V頻段電流再利用達靈頓寬頻功率放大器研製 85
3-4-1 研究現況 85
3-4-2 應用傳輸線型變壓器之V頻段電流再利用達靈頓寬頻功率放大器 88
3-4-3 電路模擬與量測結果 102
3-4-4 結果比較與討論 114
第四章可應用於調頻連續波技術之K頻段前端發射機研製 117
4-1 調頻連續波雷達簡介 117
4-2 壓控振盪器簡介 121
4-3 可應用於調頻連續波技術之K頻段前端發射機研製 123
4-3-1 研究現況 123
4-3-2 系統評估 124
4-3-3 可應用於調頻連續波技術之K頻段前端發射機設計 125
4-3-4 電路模擬與量測結果 130
4-3-5 結果比較與討論 140
第五章結論 142
5-1 結論 142
5-2 未來方向 143
參考文獻 144

參考文獻

[1] J. M. Rollett, “Stability and power gain invariants of linear two ports,” IRE Trans. on Circuit Theory, vol.9, no.1, pp. 29–32, Mar. 1962.
[2] M. L. Edwards and J. H. Sinsky, “A new criterion for linear 2-port stability using a single geometrically derived parameter,” IEEE Trans. Microw. Theory Tech., vol. 40, no. 12, pp. 2303–2311, Dec. 1992.
[3] J. R. Long, “Monolithic transformers for silicon RFIC design,” IEEE J. Solid-State Circuits, vol. 35, no. 9, pp. 1368–1382, Sept. 2000.
[4] I. Aoki, S. D. Kee, D. B. Rutledge, and A. Hajimiri, “Distributed active transformer–a new power-combining and impedance-transformation technique,“ IEEE Trans. Microw. Theory Tech., vol. 50, no. 1, pp. 316–331, Jan. 2002.
[5] P. Haldi, D. Chowdhury, P. Reynaert, G. Liu, and A. M. Niknejad, “A 5.8 GHz 1 V linear power amplifier using a novel on-chip transformer power combiner in standard 90 nm CMOS,” IEEE J. Solid-State Circuits,, vol. 43, no. 5, pp. 1054–1063, May 2008.
[6] K. H. An, O. Lee, H. Kim, D. H. Lee, J. Han, K. S. Yang, Y. Kim, J. J. Chang, W. Woo, C.-H. Lee, H. Kim, and J. Laskar, “Power-combining transformer techniques for fully-integrated cmos power amplifiers,” IEEE J. Solid-State Circuits, vol. 43, no. 5, pp. 1064–1075, May 2008.
[7] Y.-N. Jen, J.-H. Tsai, T.-W. Huang, and H. Wang, “Design and analysis of a 55–71-GHz compact and broadband distributed active transformer power amplifier in 90-nm cmos process,” IEEE Trans. Microw. Theory Tech., vol. 57, NO. 7, Jul. 2009.
[8] T. LaRocca, J. Y.-C. Liu, and M.-C. F. Chang, “60 GHz CMOS amplifiers using transformer-coupling and artificial dielectric differential transmission lines for compact design,” IEEE J. Solid-State Circuits, vol. 44, no. 5, pp. 1425–1435, May 2009.
[9] J. Oh, B. Ku, and S. Hong, “A 77-GHz CMOS power amplifier with a parallel power combiner based on transmission-line transformer,” IEEE Trans. Microw. Theory Tech., vol. 61, no. 7, pp. 2662–2669, Jul. 2013.
[10] Z. Xu, Q.-J. Gu, and M.-C. F Chang, “A 100–117 GHz W-band CMOS power amplifier with on-chip adaptive biasing,” IEEE Microw. Wireless Compon. Lett., vol. 21, no. 10, pp. 547–549, Oct. 2011.
[11] Q.-J. Gu, Z. Xu, and M.-C. F Chang, “Two-way current-combining W-band power amplifier in 65-nm CMOS," IEEE Trans. Microw. Theory Tech., vol. 60, no. 5, pp. 1365–1374, May 2012.
[12] Jerry Sevick, Transmission Line Transformers, 4th edition, SciTech Publishing, 2001.
[13] G. Guanella, “New method of impedance matching in radio-frequency circuits,” Brown-Boveri Rev., vol. 31, pp. 327–329, Sept. 1944.
[14] C. L. Ruthroff, “Some broadband transformers,” Proc. IRE, vol. 47, pp. 1337–1342, Aug. 1959.
[15] M. Engels, R. H. Jansen, W. Daumann, R. M. Bertenburg, and F.-J. Tegude, ”Design methodology, measurement and application of MMIC transmission line transformers,” in Proc. IEEE Int. Microw. Symp. Dig., May 16–20, 1995, Vol.3, pp.1635–1638.
[16] J. Horn, G. Boeck, “Integrated transmission line transformer,” in Proc. IEEE Int. Microw. Symp. Dig., Jun. 6–11, Vol.1, pp. 201–204.
[17] D. H. Lee, D. Baek, H. Kim, and S. Hong, “An on-chip low loss 1:9 transmission line transformer and its model,” Microw. Opt. Tech. Lett., vol. 48, no. 10, pp. 1936–1940.
[18] R. F. Sobrany and I. D. Robertson, “Ruthroff transmission line transformers using multilayer technology,” 33rd European Microwave Conference (EuMC), Munich, Germany, Oct. 7–9, 2003, pp.559–562.
[19] T. A. Winslow, “Ultra broadband MMIC impedance transformer,” 41st European Microwave Conference (EuMC), Manchester, Oct. 10–13, 2011, pp.854–857.
[20] H.-Y. Chung, Y.-C. Hsu, H.-K. Chiou, D.-C. Chang, and Y.-Z. Juang, “Broadband and low-loss Ruthroff-type transmission line transformer in integrated passive devices technology,” in Proc. IEEE Int. Microw. Symp. Dig., Jun. 17–22, 2012, pp.1–3.
[21] J. Roderick, and H. Hashemi, “A 0.13µm CMOS power amplifier with ultra-wide instantaneous bandwidth for imaging applications,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 8–12, 2009, pp. 374–375.
[22] H.-Y. Liao, M.-W. Pan and H.-K. Chiou, “Fully-integrated CMOS class-E power amplifier using broadband and low-loss 1:4 transmission-line transformer,” Electron. Lett., vol. 46, no. 22, pp. 1490–1491,Oct. 2010.
[23] T. Nakatani, J. Rode, D. F. Kimball, L. E. Larson, and P. M. Asbeck, “Digitally-controlled polar transmitter using a watt-class current-mode class-D CMOS power amplifier and Guanella reverse balun for handset applications,” IEEE J. Solid-State Circuits, vol. 47, no. 5, pp. 1104–1112, May 2012.
[24] H.-K. Chiou and H.-Y. Chung, “2.5–7 GHz single balanced mixer with integrated Ruthroff-type balun in 0.18 µm CMOS technology,” Electron. Lett., vol. 49, no. 7, pp. 474–475, Mar. 2013.
[25] H.-Y. Chung, C.-W. Kuo, and H.-K. Chiou, “A full X-band power amplifier with an integrated Guanella-type transformer and a predistortion linearizer in 0.18-µm CMOS,” Microw. Opt. Tech. Lett., vol. 55, no. 9, pp. 2229–2232, Sep. 2013.
[26] D. M. Pozar, Microwave Engineering, 3rd edition,John Wiley & Sons, 2004
[27] C. Lu, A.-V. H. Pham, M. Shaw, and C. Saint, “Linearization of CMOS broadband power amplifiers through combined multigated transistors and capacitance compensation,” IEEE Trans. Microw. Theory Tech., vol. 55, no. 11, pp. 2320–2328, Nov. 2007.
[28] B. Sewiolo, G. Fischer, and R. Weigel, ”A 12-GHz high-efficiency tapered traveling- wave power amplifier with novel power matched cascode gain cells using SiGe HBT transistors,” IEEE Trans. Microw. Theory Tech., vol. 57, no. 10, pp. 2329–2336, Oct. 2009.
[29] H.S. Kim, K.Y. Kim, W.Y. Kim, Y.S. Noh, I.B. Yom, I.Y. Oh, and C.S. Park, “SiGe MMIC power amplifier with on-chip lineariser for X-band applications, ” Electron. Lett., vol. 45, no. 20, pp. 1036–1037 , Sep. 2009.
[30] P.-S. Chi, Z.-M. Tsai, J.-L. Kuo, K.-Y. Lin, and H. Wang, “An X-band, 23.8-dBm fully integrated power amplifier with 25.8% PAE in 0.18-μm CMOS technology,” 40th European Microwave Conference (EuMC), Paris, France, Sep. 28–30, 2010, pp.1678–1681.
[31] H. Wang, C. Sideris, and A. Hajimiri, “A CMOS broadband power amplifier with a transformer-based high-order output matching network,” IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2709–2722, Dec 2010.
[32] B.-H. Ku, S.-H. Baek, and S. Hong, “A wideband transformer-coupled CMOS power amplifier for X-band multifunction chips,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 6, pp. 1599–1609, Jun. 2011.
[33] Y.-C. Hsu, Y.-S. Chen, T.-C. Tsai and K.-Y. Lin “A K-band CMOS cascode power amplifier using optimal bias selection methodology, ” in Proc. Asia-Pacific Microw. Conf. (APMC), Melbourne, Dec. 5–8, 2011 , pp. 793–796
[34] H. Zhang and E. Sánchez-Sinencio, “Linearization techniques for CMOS low noise amplifiers: a tutorial,” IEEE Trans. Circuits and Syst. I: Reg. Papers, vol. 58, no. 1, pp. 22–36, Jan. 2011.
[35] L. R. Kahn, “Single-sideband transmission by envelope elimination and restoration” in Proc. I.R.E., vol. 40, no. 1, pp. 803–806, Jul. 1952.
[36] J.-H. Tsai, H.-Y. Chang, P.-S. Wu, Y.-L. Lee, T.-W. Huang, and H. Wang “Design and analysis of a 44-GHz MMIC low-loss built-in linearizer for high-linearity medium power amplifiers,” IEEE Trans. Microw. Theory Tech., vol. 54, no. 6, pp. 2487–2496, Jun. 2006.
[37] J.-H. Tsai, C.-H. Wu, H.-Y. Yang, and T.-W. Huang “A 60 GHz CMOS power amplifier with built-in pre-distortion linearizer,” IEEE Microw. Wireless Compon. Lett., vol. 21, no. 12, pp. 676–678, Dec. 2011.
[38] Y.-N. Jen, J.-H. Tsai, C.-T. Peng, and T.-W. Huang, “A 20 to 24 GHz +16.8 dBm fully integrated power amplifier using 0.18-μm CMOS process,” IEEE Microw. Wireless Compon. Lett., vol. 19, no. 1, pp. 42–44, Jan. 2009.
[39] T. Yao, M. Q. Gordon, K. K. W. Tang, K. H. K. Yau, M.-T. Yang, P. Schvan, and S. P. Voinigescu, “Algorithmic design of CMOS LNAs and PAs for 60-GHz radio, ” IEEE J. Solid-State Circuits, vol. 42, no. 5, pp. 1044–1057, May 2007.
[40] C.-H. Lin and H.-Y. Chang, “A broadband injection-locking class-E power amplifier,” IEEE Trans. Microw. Theory Tech., vol. 60, no. 10, pp. 3232–3242, Oct. 2012
[41] X. Guan and A. Hajimiri, “ A 24 GHz CMOS front-end,” IEEE J. Solid State Circuits, vol. 39, no.2, pp. 368–373, Feb. 2004.
[42] J.-W. Lee and S.-M. Heo, “A 27 GHz, 14 dBm CMOS power amplifier using 0.18 μm common-source MOSFETs,” IEEE Microw. Wireless Compon. Lett., vol. 18, no. 11, pp. 755–757, Nov . 2008.
[43] A. Vasylyev, P. Weger and W. Simburger, “Ultra-broadband 20.5–31 GHz mono lithically-integrated CMOS power amplifier,” Electron. Lett., vol. 41, no. 23, pp.1281–1282, Nov 2005.
[44] P.-C. Huang, J.-L. Kuo, Z.-M. Tsai, K.-Y. Lin and H. Wang, “A 22-dBm 24-GHz power amplifier using 0.18-μm CMOS technology,” in Proc. IEEE Int. Microw. Symp. Dig., May 23–28, 2010, pp. 248–251.
[45] J.-W. Lee and B.-S. Kim, “A K-band high-voltage four-way series-bias cascode power amplifier in 0.13 μm CMOS,” IEEE Microw. Wireless Compon. Lett., vol. 20, no. 7, pp. 408–410, Jul. 2010.
[46] P.-C. Huang, K.-Y. Lin and H. Wang, “A 4–17 GHz Darlington cascode broadband medium power amplifier in 0.18 μm CMOS technology,” IEEE Microw. Wireless Compon. Lett., vol. 20, no. 1, pp. 43–45, Jan. 2010.
[47] K.-C. Lin, H.-K. Chiou, K.-H. Chien, T.-Y. Yang, P.-C. Wu, C.-L. Ko and Y.-Z. Juang, “A 4.2-mW 6-dB gain 5–65-GHz gate-pumped down-conversion mixer using Darlington cell for 60-GHz CMOS receiver,” IEEE Trans. Microw. Theory Tech., vol. 61, no. 4, pp. 1516–1522, Apr. 2013.
[48] K. Krishnamurthy, R. Vetury, S. Keller, U. Mishra, M. J. W. Rodwell, and S. I. Long, “Broadband GaAs MESFET and GaN HEMT resistive feedback power amplifiers,” IEEE J. Solid-State Circuits, vol. 35, pp.1285–1292, Sep. 2000.
[49] K. W. Kobayashi, “Linearized darlington cascode amplifier employing GaAs PHEMT and GaN HEMT techonologies,” IEEE J. Solid-State Circuits, vol. 42, no. 10, pp. 2116–2122, Oct. 2007.
[50] S.-H. Weng, H.-Y. Chang and C.-C. Chiong, “Design of a 0.5–30 GHz Darlington amplifier for microwave broadband applications,” in Proc. IEEE Int. Microw. Symp. Dig., Anaheim, May 23–28, 2010, pp.137–140.
[51] P.-C. Huang, Z.-M. Tsai, K.-Y. Lin, and H. Wang “A 17–35 GHz broadband, high Efficiency PHEMT power amplifier using synthesized transformer matching technique,” IEEE Trans. Microw. Theory Tech., vol. 60, no. 1, pp. 112–119, Jan. 2012.
[52] S. Pinel, S. Sarkar, P. Sen, B. Perumana, D. Yeh, D. Dawn, and J. Laskar, “A 90 nm CMOS 60 GHz radio,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 3–7, 2008, pp. 130–131.
[53] M. Tanomura, Y. Hamada, S. Kishimoto, M. Ito, N. Orihashi, K. Maruhashi, and H. Shimawaki, “TX and RX front-ends for 60GHz band in 90nm standard bulk CMOS,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 3–7, 2008, pp. 558–635.
[54] N. Kurita and H. Kondoh, “60GHz and 80GHz wideband power amplifier MMICs in 90nm CMOS technology,” in Proc. IEEE Radio Frequency Integrated Circuits Symp., Jun. 7–9, 2009, pp.39–42.
[55] J.-H. Tsai, Y.-L. Lee, T.-W. Huang, C.-M. Yu, J. G. J. Chern, “A 90-nm CMOS broadband and miniature Q-band balanced medium power amplifier,” in Proc. IEEE Int. Microw. Symp. Dig., Honolulu, HI, Jun. 3–8, 2007, pp.1129–1132.
[56] D. Chowdhury, P. Reynaert, and A. M. Niknejad,”A 60 GHz 1V + 12.3 dBm transformer -coupled wideband PA in 90nm CMOS,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 3–7, 2008, pp. 560–635.
[57] W. L. Chan and J. R. Long, “A 58–65 GHz neutralized CMOS power amplifier with PAE above 10% at 1-V Supply,” IEEE J. Solid-State Circuits, vol. 45, no. 3, pp. 554–564, Mar. 2010.
[58] C.-Y. Cha and S.-G. Lee, “A 5.2-GHz LNA in 0.35-µm CMOS utilizing inter-stage series resonance and optimizing the substrate resistance,” IEEE J. Solid-State Circuits, vol. 38, no. 4, pp. 669–672, Apr. 2003.
[59] S. A. Z. Murad, R. K. Pokharel, R. Sapawi, H. Kanaya, and K. Yoshida, “High efficiency, good linearity, and excellent phase linearity of 3.1–4.8 GHz CMOS UWB PA with a current-reused technique,” IEEE Trans. Consumer Electron., vol. 56, no. 3, pp. 1241–1246, Aug. 2010.
[60] V. Giammello, E. Ragonese, and G. Palmisano “A transformer-coupling current-reuse SiGe HBT power amplifier for 77-GHz automotive radar,” IEEE Trans. Microw. Theory Tech., vol. 60, no. 6, pp. 1676–1683, Jun. 2012.
[61] J. Lee, Y.-A. Li, M.-H. Hung, and S.-J. Huang “A fully-integrated 77-GHz FMCW radar transceiver in 65-nm CMOS technology,” IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2746–2756, Dec. 2010.
[62] A. Hajimiri and T. H. Lee, “A general theory of phase noise in electrical oscillators,” IEEE J. Solid-State Circuits, vol. 33, no. 2, pp. 179–194, Feb. 1998.
[63] W.-H. Hung, H.-S. Chen, S.-H. Chou, and L.-H. Lu, “An 18dBm transmitter frontend with 29% PAE for 24GHz FMCW radar applications,” in Proc. IEEE Radio Frequency Integrated Circuits Symp, Jun. 17–19, 2012, pp.137–140.
[64] J. Li, Y.-Z. Xiong, W. L. Goh, and W. Wu “A 27–41 GHz frequency doubler with conversion gain of 12 dB and PAE of 16.9%,” IEEE Microw. Wireless Compon. Lett., vol. 22, no. 8, pp. 427–429, Aug. 2012.
[65] L. Wang, Y.-Z. Xiong, B. Zhang, S.-M. Hu, and T.-G. Lim, “Millimeter-wave frequency doubler with transistor grounded-shielding structure in 0.13-µm SiGe BiCMOS technology,” IEEE Trans. Microw. Theory Tech., vol. 59, no. 5, pp. 1304–1310, May 2011.
[66] D. Ozis, N. M. Neihart, and D. J. Allstot,” Differential VCO and passive frequency doubler in 0.18um CMOS for 24GHz applications,” in Proc. IEEE Radio Frequency Integrated Circuits Symp, Jun. 11–13, 2006, pp.1–4.
[67] J. Yang, C.-Y. Kim, D.-W. Kim, and S. Hong, “Design of a 24-GHz CMOS VCO With an asymmetric-width transformer,” IEEE Trans. Circuits and Syst. II: Exp. Briefs, vol. 57, no. 3, pp. 173–177, Mar. 2010.
[68] A. Natarajan, A. Komijani, and A. Hajimiri, “Fully integrated 24-GHz phased-array transmitter in CMOS,” IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2502–2514, Dec. 2005.
[69] Y. Cao, M. Tiebout, V. Issakov, “A 24GHz FMCW radar transmitter in 0.13 μm CMOS” in Proc. 34th European Solid-State Circuits Conference (ESSCIRC), Sept. 15–19, 2008, pp.498–501.
[70] B. Razavi, Design of analog CMOS integrated circuits, McGraw-Hill, 2001.
[71] R. Ludwig and G. Bogdanov, RF Circuit Design: Theory & Applications, 2nd Edition, Prentice Hall, 2008.
[72] 廖顯原，「應用於矽基功率放大器之傳輸線變壓器與穿透矽通孔之研究」，國立中央大學，博士論文，民國100年。
[73] 陳瑋強，「Ku/K頻段壓控振盪器及注入鎖定除頻器暨毫米波fT-倍頻電路壓控振盪器與寬頻混頻器之研製」，國立中央大學，碩士論文，民國98年。
[74] 黃亭堯，「應用傳輸線變壓器與功率結合技術於全積體化功率放大器之研究」，國立中央大學，碩士論文，民國100年。
[75] 林喬盛，「應用功率結合變壓器之達靈頓功率放大器與X頻段pHEMT製程功率放大器研製」，國立中央大學，碩士論文，民國101年。
[76] 鄭淵勵，「 C/V頻段全積體整合矽製程之寬頻功率放大器研製」，國立中央大學，碩士論文，民國101年。
[77] 張盛富，張嘉展，無線通訊射頻晶片模組設計-射頻晶片篇，全華圖書股份有限公司，民國96年。

指導教授

邱煥凱(Hwann-Kaeo Chiou)

審核日期

2013-8-13

推文