應用於電容陣列區塊之良率導向地鐵式繞線法

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姓名

江哲君(Che-Chun Chiang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

應用於電容陣列區塊之良率導向地鐵式繞線法
(Subway-CABC: A Yield-aware Subway Router for Capacitor Array Block Creation)

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至系統瀏覽論文 ( 永不開放)

摘要(中)

對於在類比積體電路電容器的實現，它是連接對應於總量的單元電容器。互連的寄生電容大大地影響了電容比率並且導致性能的退化。因此，寄生電容需要考慮和良好的控制。在這篇論文中，Subway繞線，其擺置互連在MIM電容下，加入了我們的電容陣列塊創（CABC）。它具有多種強大的功能，包括績效補償和降低錯配和更低的面積，進步良率高。
兩個電路的例子，8-位元SAR ADC和弗萊舍 - 湖人開關電容濾波器，用於演示的性能Subway繞線器。結果表明，在這兩個電路中，電容率是良好匹配，並比以前更好的性能。

摘要(英)

For the implementation of capacitors in the analog integrated circuits, it is to connect the unit capacitors corresponding to the total amount. The parasitic capacitance of interconnects greatly affects the Capacitance Ratio and induces the performance degradation. Hence, parasitic capacitances need to be considered and well controlled. In this thesis, a subway routing style, which places the interconnects under the MiM capacitors, is proposed for our capacitor array block creators (CABC). It exhibits several powerful features including performance compensation and mismatch reduction and with less area, in turns, high yield.
Two circuit examples, 8-bit SAR ADC and Fleischer-Laker switched-capacitor filter, are used to demonstrate the performance of subway router. It is shown that, in both circuits, capacitance ratios are good matched and better performance than the previous.

關鍵字(中)

★ 電容陣列
★ 類比繞線

關鍵字(英)

★ Capacitor Array
★ Analog Router

論文目次

中文摘要 i
Abstract ii
誌謝 iii
目錄 iv
圖目錄 v
表目錄 vii
第1章緒論 1
1-1 動機與背景 1
1-2 論文組織 2
第2章電容布局設計的概念 3
2-1 電容的Layout圖及長寬計算方法 3
2-2 電容不匹配的原因 4
2-3 導線寄生模型 5
第3章電容陣列的繞線 8
3-1 繞線 8
3-2 Subway 8
3-3 耦合電容的避免 12
3-4 避免繞線時產生的不匹配 14
第4章實驗及分析 16
4-1 SAR ADC 16
4-2 SAR繞線後寄生電容的分析 17
4-3 Fleischer-Laker 19
4-4 Fleischer-Laker 繞線後寄生電容的分析 19
第5章結論 21
參考文獻 22

參考文獻

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指導教授

陳竹一(Jwu-E Chen)

審核日期

2013-11-28

推文