以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：32

、訪客IP：3.133.109.251

姓名	廖健男(Chien-nan Liao)  查詢紙本館藏	畢業系所	電機工程學系
論文名稱	低功率損耗功率垂直型雙擴散金氧半場效應電晶體 (Low Power Loss Power Vertical Double-diffused MOSFET)
相關論文	★ 表面電漿共振效應於光奈米元件之數值研究 ★ 金氧半電容元件的暫態模擬之數值量測 ★ 雙載子電晶體在一維和二維空間上模擬的比較 ★ 改善後的階層化不完全LU法及其在二維半導體元件模擬上的應用 ★ 一維雙載子接面電晶體數值模擬之驗證及其在元件與電路混階模擬之應用 ★ 階層化不完全LU法及其在準靜態金氧半場效電晶體電容模擬上的應用 ★ 探討分離式簡化電路模型在半導體元件模擬上的效益 ★ 撞擊游離的等效電路模型與其在半導體元件模擬上之應用 ★ 二維半導體元件模擬的電流和電場分析 ★ 三維半導體元件模擬器之開發及SOI MOSFET特性分析 ★ 元件分割法及其在二維互補式金氧半導體元件之模擬 ★ 含改良型L-ILU解法器及PDM電路表述之二維及三維元件數值模擬器之開發 ★ 含費米積分之高效率載子解析模型及其在元件模擬上的應用 ★ 量子力學等效電路模型之建立及其對元件模擬之探討 ★ 適用於二維及三維半導體元件模擬的可調變式元件切割法 ★ 整合式的混階模擬器之開發及其在振盪電路上的應用
檔案	[Endnote RIS 格式]    [Bibtex 格式]    [相關文章]   [文章引用]   [完整記錄]   [館藏目錄]   [檢視]  [下載] 本電子論文使用權限為同意立即開放。 已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。 請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。
摘要(中)	隨著世界的進步與發展導致大量自然資源的使用及能源的需求，使得能源快速消耗，更因為自然資源的有限，因此如何有效利用能源、節省不必要的能源開支成為日後相當重要的問題。 功率金氧半場效應電晶體被大量應用在許多方面，包括消費性電子產品、電腦、通訊、汽車電子及家電，由於節能意識的抬頭，如何降低元件的功率損耗成為元件設計者的目標。對低壓功率金氧半電晶體，提出羽翼狀晶胞設計其結合了方型及線型晶胞。羽翼狀晶胞移除部份晶胞間的複晶矽面積，因此增加了通道密度及電流路徑，導通電阻值可因此降低。羽翼狀晶胞的設計可被應用在平面式閘極及溝槽式閘極的功率金氧半場效應電晶體。 對高壓功率金氧半電晶體，由於寄生接面場效應電晶體電阻，長閘極是不可避免的，因而造成元件的低切換速度及高切換損耗。針對此問題提出結合分離式閘極及浮接np型井區，與使用全面性離子佈植的功率金氧半場效電晶體的設計來改善元件的切換問題。分離式閘極移除部份的閘極面積來達到提高切換速度的目的，而np型井區則避免了電場的聚集。全面性離子佈植則藉由提高表面的濃度，使閘極縮短時能抑制寄生電阻的增加。
摘要(英)	With the progress and development of the world, it results in a great mount of natural resources use and the energy requirement and rapid consumption of the energy. Due to the limited natural resources, how to use the energy efficiently without wasting becomes an important question. Power metal oxide semiconductor field effect transistor are used widely in a lot of fields includes consumer electronics, computers, communication, car electronics, and home appliances. Due to the energy saving, how to reduce the power loss becomes a target for devices designers. For low voltage power VDMOSFETs, it proposed wing cell design, combining the square cell and linear cell. The wing cell removes a part of the poly area between each cell. Therefore, both the channel density and current path can be increased. Consequently, the on-resistance can be reduced efficiently. The wing cell design can be used to the planar-gate and trench-gate power VDMOSFETs. For high voltage power VDMOSFETs, the long gate length can not be avoided because the parasitic JFET resistance. Due to this reason, low switching speed and high switching loss occur. In order to decrease them, a split gate with floating np-well power VDMOSFET and overall implant power VDMOSFET are proposed. The split gate with floating np-well power VDMOSFET removes a part of gate area. However, the electric field crowding and high on-resistance were happened at the same time. Consequently, a floating np-well is incorporated to solve it. On the other hand, shortening the gate length is a more easy way to improve switching speed and switching loss. But, the parasitic JFET resistance increases rapidly with the shortened gate length. Therefore, a high concentration layer is required to restrain the parasitic JFET resistance while shortening the gate length.
關鍵字(中)	★ 功率損耗 ★ 邊緣區 ★ 閘極電荷 ★ 導通電阻 ★ 功率金氧半電晶體	關鍵字(英)	★ termination ★ gate charge ★ on resistance ★ power MOSFET ★ power loss
論文目次	Chapter 1 Introduction of Power Metal Oxide Semiconductor Field Effect Transistors 1-1 History of Power Electronics…………………...…………..…………..…1 1-2 Power Semiconductor Devices………………………………............……2 1-3 Power Vertical Double-diffused Metal Oxide Semiconductor Field Effect Transistor……………………………………………………....6 1-4 The Characteristics of Power VDMOSFETs……………………...…15 1-4-1 On-state Resistance………...………..…………………...…………15 1-4-2 Gate Charge……………………………..……….…………………...20 1-4-3 Avalanche Breakdown………………..……….…………………...22 Chapter 2 Low On-State Resistance Wing-cell Power VDMOSFET Design 2-1 Planar-Gate Power VDMOSFET……………………...……….………27 2-1-1 Device Design………………………………….…………………….27 2-1-2 Experiment Results and Discussion…………...…………………30 2-2 Trench-Gate Power VDMOSFET…………………….…………….….33 2-2-1 Device Design………………………………………………………..33 2-2-2 Experiment Results and Discussions………………...…………..36 Chapter 3 Low Gate Charge Power VDMOSFETs Design 3-1 Power VDMOSFET with Overall Implant……………..………….....40 3-1-1 Device structure and fabrication……………………...…….…….42 3-1-2 Results and Discussion…...…………………...……………………45 3-2 Power VDMOSFET with Partial Implant……………..……….…….50 3-2-1 Device structure and fabrication………...………………………..50 3-2-2 Simulated Results and Discussion………………………………..53 3-3 Power VDMOSFET with Split Gate Floating NP-well Design…..55 3-3-1 The Performances of SG Structure with Different Design…...55 3-3-2 Device Fabrication………………………………………...………...59 3-3-3 The Simulated and Experimental Results Discussion………...63 Chapter 4 The Termination of Power VDMOSFET 4-1 The Termination Structure……………...……….………………..……..69 4-2 Numerical Analysis of Surface Potential and Electric Field……..71 4-3 The Simulated Results and Discussion……………...……..……..…....74 4-3-1 Ring Depth, RD………………………………………………………74 4-3-2 Field Oxide Thickness, TOX…………………………..……………76 4-3-3 Spacing Between Main Junction and Ring, WF……………..…77 4-3-4 Ring Width, WR……………………………….……………………..79 4-3-5 First Field Plate Width, WFP1………………………………...……80 4-3-6 Second Field Plate Width, WFP2…………………………………..82 4-4 Multi FFLRs-FPs Design……………………..………………….………..85 4-5 Comparison of FFLR with and without FP……………..…..………..87 Chapter 5 Study of Drain Alloy for Antimony Substrate Vertical High Voltage Power Metal Oxide Semiconductor Field Effect Transistors 5-1 The Source-Drain Voltage………………………….…………………….90 5-2 Out-doping Phenomenon in Power VDMOSFETs……….....……...91 5-3 The Experimental and Results…..............………..……….…………….93 Conclusion……………………………………………...........................….……96 Reference...............................................................................................................98
參考文獻	[1]A. Lidow, T. Herman, H.W. Collins, “POWER MOSFET TECHNOLOGY”, IEEE, pp.79-83, 1979. [2]B.J. Baliga, “POWER SEMICONDUCTOR DEVICES”, PWS PUBLISHING COMPANY, 1996. [3]B.J. Baliga, “EVOLUTION AND STATUS OF SMART POWER TECHNOLOGY”, IEEE Applied Power Electronics Conference and Exposition, pp.18-21, 1993. [4]B.J. Baliga, “Trends in Power Semiconductor Devices”, IEEE TRANS. ELECTRON DEVICES, VOL. 43, 1998. [5]M.H. Rashid, “POWER ELECTRONICS CIRCUITS, DEVICES, AND APPLICATIONS”, Pearson Education International, 2004. [6]B.J. Baliga, “An Overview of Smart Power Technology”, IEEE TRANS. ELECTRON DEVICES, VOL. 38, 1991. [7]B.J. Baliga, “The Future of Power Semiconductor Device Technology”, IEEE Proceedings of the IEEE, VOL. 89, 2001. [8]D.A. Grant, J. Gowar, “POWER MOSFET：Theory and Application”, A Wiley-Interscience Publication, 1989. [9]M.L. Tarng, “ON-RESISTANCE CHARACTERIZATION OF VDMOS POWER TRANSISTORS”, IEEE Int. Electron Device Meet (IEDM), pp.429-433, 1981. [10]J. Fernandez, S. Hidalgo, J. Paredes, J. Rebollo, J. Millan and F. S. Mestres, “An ON-Resistance Closed Form for VDMOS Devices”, IEEE ELECTRON DEVICE LETT., VOL. 10, 1989. [11]R.P. Zingg, “On the Specific On-Resistance of High-Voltage and Power Devices”, IEEE TRANS. ELECTRON DEVICES, VOL. 51, pp.492-499, 2004. [12]C.M. Hu, M.H. Chi and V.M. Patel, “Optimum Design of Power MOSFET’s”, IEEE TRANS. ELECTRON DEVICES, VOL.ED-31, pp.1693-1700, 1984. [13]I. Yoshida, M. Morikawa, S. Ohtaka and T. Okabe, “LOW ON-RESISTANCE AND HIGH-RELIABILITY POWER MOSFETS”, IEEE Int. Power Electronics Specialists Conference (PESC), pp.674-680, 1988 [14]C. Fink, J. Schulze, I. Eisele, W. Hansch, W. Werner and W. Kanert, “Vertical Power-MOSFETs with Local Channel Doping”, IEEE Int. Electron Device Meet (IEDM), pp.71-74, 2000. [15]H. Yilmaz, I. Hshieh, M. Chang and J.V.D. Linde, “2.5 MILLION CELL/INCH2, LOW-VOLTAGE DMOSFET TECHNOLOGY”, IEEE, pp.513-518, 1991. [16]R.J.E. Hueting, E.A. Hijzen, A.W. Ludikhuize and M.A.A. in’t Zandt, “Gate-Drain Charge Analysis for Switching in Power Trench MOSFETs”, IEEE TRANS. ELECTRON DEVICES, VOL.51, pp.1323-1330, 2004. [17]Y.C. Ren, M. Xu, J.H. Zhou and F.C. Lee, “Analytical Loss Model of Power MOSFET”, IEEE TRANS. ELECTRON DEVICES, VOL.21, pp.310-319, 2006. [18]A.Q. Huang, N.X. Sun, B. Zhang, X.W. Zhou and F.C. Lee, “Low Voltage Power Devices for Future VRM”, IEEE Int. Symposium on Power Semiconductor Devices & ICs (ISPSD), pp.395-398, 1998. [19]W. Weber, R.D. Schrimpf, R.G. Meyers, A.F. Witulski and K.F. Galloway, “Radiation Induced Changes in Power MOSFET Gate-Charge Measurement”, IEEE, pp.1673-1678. [20]S.M. Xu, C.H. Ren, P.D. Foo, Y. Liu and Y. Su, “Dummy Gated Radio Frequency VDMOSFET with High Breakdown Voltage and Low Feedback Capacitance”, IEEE Int. International Symposium on Power Semiconductor Devices & ICs (ISPSD), pp.385-388, 2000. [21]W.J. Chen, B. Zhang and Z.J. Li, “A Novel VDMOSFET Structure with Reduced Gate Charge”, IEEE, pp.1395-1398, 2005. [22]A.J. Yiin, R.D. Schrimpf and K.F. Galloway, “GATE-CHARGE MEASUREMENT FOR IRRADIATED N-CHANNEL DMOS POWER TRANSISTORS”, IEEE TRANS. ELECTRON DEVICES, VOL.38, pp.1352-1358, 1991. [23]K. Fischer and K. Shenai, “Dynamics of Power MOSFET Switching Under Unclamped Inductive Loading Conditions”, IEEE TRANS. ELECTRON DEVICES, VOL.43, pp.1007-1015, 1996. [24]K. Pinardi, U. Heinle, S. Bengtsson, J. Olsson, J.P. Colinge, “Unclamped inductive switching behaviour of high power SOI vertical DMOS transistors with lateral drain contacts”, Solid-State Electronics, 46, pp.2105–2110, 2002. [25]D. UEDA, H. TAKAGI and G. KANO, “A New Vertical Double Diffused MOSFET—The Self-Aligned Terraced-Gate MOSFET”, IEEE TRANS. ELECTRON DEVICES, VOL.ED-31, pp. 416-420, 1984. [26]H. Ikeda, H. Yoshida and T. Onikura, “High-Frequency, High-power MOS-FET”, IEEE Int. Electron Device Meet (IEDM), pp.246-249, 1982. [27]Y. Shimada, K. Kato, S. Ikeda and H. Yoshida, “Low Input Capacitance and Low Loss VD-MOSFET Rectifier Element”, IEEE TRANS. ELECTRON DEVICES, VOL.ED-29, pp.1332-1334, 1982. [28]S. Xu, K.P. Gan, P.D. Foo, Y. Su and Y. Liu, “Graded Gate VDMOSFET”, IEEE ELECTRON DEVICE LETT., VOL.21, pp.176-178, 2004. [29]T. Sakai and N. Murakami, “A New VDMOSFET Structure with Reduced Reverse Transfer Capacitance”, IEEE TRANS. ELECTRON DEVICES, VOL.36, pp.1381-1386, 1989. [30]W. Chen, B. Zhang and Z. Li, “Optimization of the VDMOSFET structure with reduced gate charge”, SEMICOND. SCI. TECHNOL., 22, pp.1033–1038, 2007. [31]V.A.K. Temple and M.S. Alder, “Calculation of diffusion curvature related avalanche breakdown in high-voltage planar p-n junctions”, IEEE TRANS. ELECTRON DEVICES, VOL.ED-22, pp.910-916, 1975. [32]V. Anantharam and K.N. Bhat, “Analytical solutions for the breakdown voltage of punched through diodes having curved junction boundaries at the edges”, IEEE TRANS. ELECTRON DEVICES, VOL.ED-27, pp.939-945, 1980. [33]M.S. Alder, V.A.K. Temple, A.P. Ferro and R.C. Rustay, “Theory and breakdown voltage for planar devices with single field limiting ring”, IEEE TRANS. ELECTRON DEVICES, VOL.ED-24, pp.107-113, 1977. [34]V.C. Kao and E.D. Wolley, “High voltage planar p-n junctions”, Proc. IEEE, VOL.55, pp.1409-1414, 1967. [35]C.B. Goud and K.N. Bhat, “Two-dimensional analysis and design considerstions of high-voltage planar junctions equipped with field plate and guard ring”, IEEE TRANS. ELECTRON DEVICES, VOL.38, pp.1497-1504, 1999. [36]T. Matsushita, T. Aoki, T. Ohtsu, H. Yamoto, H. Hayashi, M. Okayama and Y. Kawana, “Highly reliable high-voltage transistors by use of the SIPOS process”, IEEE TRANS. ELECTRON DEVICES, VOL.ED-23, pp.826-830, 1976. [37]V.A.K. Temple, “Junction termination extension (JTE), a new technique for increasing avalanche breakdown voltage and controlling surface electric fields in p-n junctions”, IEEE Int. Electron Device Meet (IEDM), pp.423-426, 1977. [38]V.A.K. Temple and W. Tantraporn, “Junction termination extension for near-ideal breakdown voltage in p-n junction”, IEEE TRANS. ELECTRON DEVICES, VOL.ED-33, pp.1601-1608, 1986. [39]J.A. Appels and H.M.J. Vaes, “High-voltage thin layer devices (Resurf devices)”, IEEE Int. Electron Device Meet (IEDM), pp.238-241, 1977. [40]R. Stengl, U. Gosele, C. Fellinger, M. Beyer and S. Walesch, “Variation of lateral doping as a field terminator for high-voltage power devices”, IEEE TRANS. ELECTRON DEVICES, VOL.ED-33, pp.426-428, 1986. [41]W.C. Lin, K. Petrosky and D. Lampe, “Estimate of increase of planar junction breakdown voltage with field limiting ring”, IEEE, pp.674-677, 1988.
指導教授	蔡曜聰(Yao-tsung Tasi)	審核日期	2010-6-29
推文	facebook   plurk   twitter   funp   google   live   udn   HD   myshare   reddit   netvibes   friend   youpush   delicious   baidu
網路書籤	Google bookmarks   del.icio.us   hemidemi   myshare