應用於醫療植入式通訊服務頻帶之分數型頻率合成器之研製

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林昆毅(Kun-Yi Lin) 查詢紙本館藏

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電機工程學系

論文名稱

應用於醫療植入式通訊服務頻帶之分數型頻率合成器之研製
(The Implementation of Fractional Frequency Synthesizer for Medical Implant Communication Service (MICS) Band)

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摘要(中)

1999 年美國聯邦通訊委員會制定了一個工作頻率的範圍在402~405MHz 並有十個頻道寬為300kHz 的無線頻帶稱作醫療植入式通訊服務。其應用的範圍適合具完全積體化的極低功耗並能在短距離下更快速的資料傳輸速度的人體植入式電子輔具。在設計講求小面積，低功率消耗的植入式視覺輔具的分數型頻率合成器的過程中，我們利用降低金屬繞線電感以增加品質因素以及降低壓控振盪器KVCO 的方式提升振盪器的相位誤差的效能。最後使用TMSC 0.18um 標準CMOS 製程使用1.5V 的系統電壓實現了一個核心面積為1.56mm2，功率消耗為2.93mW，佈局後模擬頻率鎖定時間小於100us 而量測之相位雜訊在160kHz 處為-100dBc/Hz 並符合MICS 系統的分數型頻率合成器。

摘要(英)

The 402-405MHz medical implant communication service (MICS) has been allocated by US Federal Communication Commission (FCC) in 1999 to provide 10 channels with 300 kHz bandwidth, of which application is suitable for full integration human implantable prosthetics with ultra-low power consumption and higher data rate in a short distance. In the thesis, a fractional frequency synthesizer is designed for implantable visual prosthetics which aims at small area and low power consumption, reduction of parasitic resistance of metal spiral inductor and low KVCO of voltage-controlled oscillator so as to realize an MICS-compatible fractional frequency synthesizer with core area of 1.56mm2, power consumption of 2.93mW, post-layout-simulation locking time of less than 100us, and measured phase noise of -100dBc/Hz at 160kHz offset for 1.5V supply voltage in TSMC 0.18 mm standard CMOS process.

關鍵字(中)

★ 鎖相迴路
★ 非整數型頻率合成器
★ 醫療植入式通訊服務
★ 和差積分調變器

關鍵字(英)

★ phase-locked loop (PLL)
★ fractional frequency synthesizer
★ Medical Implant Communication Service (MICS)
★ sigma-delta modulator

論文目次

摘要 i
Abstract ii
致謝 iii
目錄 iv
圖目錄 vi
表目錄 ix
第一章緒論 1
1.1 研究背景 1
1.2 研究動機 2
1.3 論文架構 6
第二章鎖相迴路之基本理論與電路 7
2.1 整數型鎖相迴路 7
2.1.1 壓控振盪器 8
2.1.2 除頻器 15
2.1.3 相位頻率偵測器 17
2.1.4 電荷幫浦 18
2.1.5 迴路濾波器 20
2.2 分數型鎖相迴路 21
2.2.1 分數型鎖相迴路基本原理 22
2.2.2 和差調變器之介紹 23
2.2.3 多級和差調變器(MASH結構) 28
2.3 線性數學模型理論 30
2.4 鎖相迴路的行為性模擬 36
2.4.1 Matlab的Simulink軟體 36
2.4.2 Agilent的ADS軟體 39
第三章頻率合成器之實現 41
3.1 電路設計之考量 41
3.2 壓控振盪器 42
3.2.1 電感品質因數的提升 42
3.2.2 相位雜訊及功率上的最佳化 44
3.3 數位電路之設計 46
3.3.1 相位頻率偵測器 46
3.3.2 除頻器 47
3.3.3 和差調變器 48
3.3.4 位移暫存器 52
3.4 類比電路之設計 52
3.4.1 電荷幫浦 52
3.4.2 迴路濾波器 54
3.4.3 電容放大器 55
第四章晶片模擬與佈局量測 60
4.1 頻率合成器各區塊模擬結果 60
4.2 壓控振盪器的佈局後模擬結果 67
4.3 頻率合成器的佈局後模擬結果 71
4.4 晶片佈局 74
4.5 電路量測 76
4.5.1 量測考量 76
4.5.2 量測結果與討論 80
第五章結論 86
5.1 結論 86
5.2 未來展望 86
參考文獻 88

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指導教授

薛木添(Muh-Tian Shiue)

審核日期

2010-8-24

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