適用於影像編碼系統中具有壓縮率控制之嵌入式壓縮演算法

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：50

、訪客IP：3.15.143.181

姓名

陳奕成(Yi-Cheng Chen) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

適用於影像編碼系統中具有壓縮率控制之嵌入式壓縮演算法
(An Embedded Compression Algorithm with Rate Control Scheme for Video Coding System)

相關論文

★ 即時的SIFT特徵點擷取之低記憶體硬體設計	★ 即時的人臉偵測與人臉辨識之門禁系統
★ 具即時自動跟隨功能之自走車	★ 應用於多導程心電訊號之無損壓縮演算法與實現
★ 離線自定義語音語者喚醒詞系統與嵌入式開發實現	★ 晶圓圖缺陷分類與嵌入式系統實現
★ 語音密集連接卷積網路應用於小尺寸關鍵詞偵測	★ G2LGAN: 對不平衡資料集進行資料擴增應用於晶圓圖缺陷分類
★ 補償無乘法數位濾波器有限精準度之演算法設計技巧	★ 可規劃式維特比解碼器之設計與實現
★ 以擴展基本角度CORDIC為基礎之低成本向量旋轉器矽智產設計	★ JPEG2000靜態影像編碼系統之分析與架構設計
★ 適用於通訊系統之低功率渦輪碼解碼器	★ 應用於多媒體通訊之平台式設計
★ 適用MPEG 編碼器之數位浮水印系統設計與實現	★ 適用於視訊錯誤隱藏之演算法開發及其資料重複使用考量

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

隨著影像編碼技術發展，許多影像編解碼標準已廣泛應用於生活中，如MPEG-4可用於網路串流影像、 H.264/AVC 應用於高畫質影像。在這些影像編解碼標準中應用了許多的編碼技巧來提高編碼效率，如畫面內預測(Intra Prediction)，離散餘弦轉換(Discrete Cosine Transform)以及多張參考畫面(Multi-Reference Frame)。然而，這些用來提高編碼效率的技術需要大量的運算資源及記憶體頻寬。隨著半導體製程技術的演進，大量的運算資源可透過適當的硬體設計技巧或軟硬體整合的方式來解決，但大量的運算資料仍須透過對外部記憶體作存取，如H.264中移動估計(motion estimation)就必須從外部記憶體中大量存取所要參考的資料來做運算，在記憶體頻寬或容量有限的影像編碼系統中會造成設計上的一個瓶頸。嵌入式壓縮(Embedded Compression)技術可預先將資料經壓縮後再存入外部記憶體中，藉此來減少對外部記憶體的使用量。
本論文所提出的嵌入式壓縮演算法主要包含下列技術: (1) Side-Oriented Prediction (2) Adjusted Binary Code (3) Two-Level Rate Control Scheme. 應用two-level rate control 的嵌入式壓縮演算法不僅可以有效率的控制壓縮率，並且可減少因量化而導致影像品質失真的情形。實驗結果顯示本論文所提出的演算法在失真度上與未加入嵌入式壓縮演算法之前相比只有1.33%的下降，且與預期的壓縮率比較也僅有1.60%的差距。因此，在現今記憶體受限的影像編碼系統中，本演算法可提供一個有效降低記憶體頻寬及容量的方法。

摘要(英)

Owing to the rapid evolution of video coding techniques, video coding standards have been widely applied in many applications, such as MPEG-4 for streaming video on Internet and H.264/AVC for High Definition TV (HDTV). Many coding tools, including intra prediction, discrete cosine transform (DCT) and multi-reference frames (MRF) are further incorporated to improve coding efficiency. With these coding functions, great demands for computation resource and memory bandwidth are significantly increased. As the semiconductor have advanced into nano-scale technology, huge requirement of computing operation can be satisfied by proper design methodology, such as HW/SW co-design or dedicated hardware for acceleration. However, memory access operation still occupies a high percentage of whole computing profiling in H.264/AVC encoder. Therefore, memory bandwidth becomes a bottleneck in video coding systems. The embedded compression (EC) technology is widely applied to save frame memory size and bandwidth requirement.
For video coding system, the proposed EC algorithm mainly consists of three core techniques: side-oriented prediction, adjusted binary code and two-level rate control scheme. With two-level rate control scheme, not only the compression ratio (CR) can be precisely controlled, but also the visual quality is maintained. Experiment results reveal that this work achieves the PSNR drop of 1.33%, and the error between CR and Target CR (TCR) is as minor as 1.60%. Consequently, this work is quite suitable for saving memory bandwidth in video coding system.

關鍵字(中)

★ 嵌入式壓縮
★ 影像編解碼系統

關鍵字(英)

★ embedded compression
★ video coding system

論文目次

摘要…..……………………………………………………………………………. i
Abstract……………………………………………………………………………. ii
致謝........................................................................................................................... iii
Content……………………………………………………………………………. iv
List of Figures……………………………………………………………………... vi
List of Tables……………………………………………………………………… vii
Chapter 1 Introduction……………………………………………………….. 1
1.1 Motivation……………………………………………………………. 2
1.2 Thesis Organization…………………………………………………... 3
Chapter 2 Background………………………………………………………... 4
2.1 Overview of Data Compression……………………………………… 5
2.1.1 Lossless Compression………………………………………….. 5
2.1.2 Lossy Compression…………………………………………….. 6
2.1.3 Transform Coding……………………………………………… 8
2.1.4 Entropy Coding………………………………………………… 9
2.2 Overview of Video Coding System………………………………….. 10
2.2.1 The MPEG Serials……………………………………………... 11
2.2.2 The H.26x Serials………………………………………………. 13
2.2.3 Related Standards……………………….……………………… 17
2.3 Summary…………………………………………................................. 19
Chapter 3 Related Work of Embedded Compression Algorithms for Video Coding System………………………………………………………
20
3.1 Spatial Domain Embedded Compression……………...……………… 21
3.1.1 Lossy Algorithms……………………………………………… 21
3.1.2 Lossless Algorithms……………….…………………………... 24
3.2 Transform Domain Embedded Compression……………...………….. 29
3.2.1 Lossy Algorithms……………………………………………… 29
3.2.2 Lossless Approaches…………………………………………… 31
3.3 Summary………………………………………………………………….. 33
Chapter 4 Proposed EC Algorithm for Video Coding System………………. 34
4.1 Side-Oriented Prediction……………………………………………….. 35
4.2 Adjusted Binary Code………………………………………………….. 38
4.3 Codeword Truncation Scheme................................................................. 40
4.4 EC algorithm Flow Chart with Two-Level Rate Control Scheme……... 41
4.4.1 The Decoding Procedure and Data Packing Format………….... 43
4.5 Experimental Results and Discussion………………………………….. 44
4.6 Summary.................................................................................................. 46
Chapter 5 Conclusions and Future Work…………………………………… 48
References................................................................................................................. 50

參考文獻

[1] Yu-Kun Lin, et. al, "A 242mW 10mm2 1080p H.264/AVC High-Profile Encoder Chip," in Proc. International Solid-State Circuits Conference (ISSCC), 2008.
[2] Chien-Chang Lin, et. al, “A 160K Gates/4.5KB SRAM H.264 Video Decoder for HDVT application,” IEEE Journal of Solid-State Circuits Syst. (ISSCC) vol. 42, no.1, pp.170~182, Jan 2007.
[3] T.-C. Chen, S.-Y. Chien, Y.-W. Huang, C.-H. Chen, C.-Y. Chen, T.-W. Chen, and L.-G. Chen, “Analysis and architecture design of and HDTV720p 30 frames/s H.264/AVC encoder,” IEEE Trans. Circuits Syst. Video Technol., vol. 16, no. 6, pp. 673-- -688, Jun. 2006.
[4] Z. Liu, et. al, “HDTV1080p H.264/AVC Encoder Chip Design and Performance Analysis”, IEEE Journal of Solid-State Circuits., vol. 42, no.1, pp.170~182, Feb 2009.
[5] T. Nishikawa, et al., “A 60 MHz 240mW MPEG-4 video-phone LSI with 16 Mb embedded DRAM,’’ in Digest of Technical Papers of IEEE International Solid-State Circuits Conference (ISSCC), 2000, pp. 230-231.
[6] A. Beric, J. V. Meerbergen, G. D. Haan, G, and R. Sethuraman,“Memory-Centric Video Porcessing,” IEEE Trans. Circuits Syst. video Technol., vol. 18, no. 4, pp. 673-688, Jun. 2008.
[7] Bhaskaran, V. and K. Konstantinides, Image and Video Compression Standards: Algorithms and Architectures, Kluwer, 1997.
[8] http://www.vcodex.com/files/h264_overview_orig.pdf
[9] Y. Lee, C.-E. Rhee and H.-J. Lee, “A New Frame Recompression Algorithm Integrated with H.264 Video Compression,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 1621-1624, May 2007.
[10] Y.-X. Lee and T.-H. Tsai, “An efficient embedded compression algorithm using adjusted binary code method,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), pp. 2586-2589, May 2008.
[11] P. G. Howard and J. S. Vitter, “Fast and efficient lossless image compression,” in Proc. IEEE Int. Conf. Data Compression, 1993, pp. 501-510.
[12] J. Kim, and C.-M. Kyung, “A lossless embedded compression algorithm for high definition video coding,” in Proc. IEEE Int. Conf. Multimedia Expo (ICME), Jul. 2009, pp. 193–196.
[13] J. Kim, and C.-M. Kyung, “A Lossless Embedded Compression Using Significant Bit Truncation for HD Video Coding,” IEEE Trans. Circuits Syst. video Technol., vol. 20, no. 6, pp. 848-860, Jun. 2010.
[14] T. Song and T. Shimamoto, “Reference frame data compression method for H.264/AVC,” IEICE Electron. Express, vol. 4, no. 3, pp. 121–126,2007.
[15] T.-Y. Lee, “A New Frame-Recompression Algorithm and its Hardware Design for MPEG-2 Video Decoders,” IEEE Trans. CSVT, vol. 13, no. 6, pp. 529-534, June 2003.
[16] T.-C. Wu, Y.-H. Chen, K.Li, and C.-Y. Lee, “A Novel Embedded Bandwidth-Aware Frame Compressor for Mobile Video Applications,” in Proc. Int. Symp. Intell. Signal Process. Commun. Syst. (ISPACS), Dec. 2009,pp. 1–4.
[17] W.-Y. Chen, L.-F. Ding, P.-K. Tsung, and L.-G. Chen, “Architecture design of high performance embedded compression for high definition video coding,” in Proc. IEEE Int. Conf. Multimedia Expo (ICME), Apr. 2008, pp. 825–828.
[18] C.-C. Cheng, P.-C. Tseng, and L.-G. Chen, “Multimode embedded compression codec engine for power-aware video coding system,” IEEE Trans. Circuits Syst. Video Technol., vol. 19, no. 2, pp. 141–150, Feb.2009.

指導教授

蔡宗漢(Tsung-Han Tsai)

審核日期

2010-8-27

推文