應用於三維積體電路之記憶體架構探索與評估方法

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陳詠孝(Yong-Xiao Chen) 查詢紙本館藏

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電機工程學系

論文名稱

應用於三維積體電路之記憶體架構探索與評估方法
(Architecture Exploration and Evaluation Methods for Memories in 3D ICs)

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摘要(中)

利用矽穿孔(TSV)方法的三維整合技術(3D integration technology)，已被公認為未來的晶片設計技術之一。相較於傳統的二維的積體電路與整合技術，三維整合技術可以提供更多的好處，例如：減少外觀的面積、減少導線長度、高效能、較低的功率消耗、高功能性、異質整合等等的好處。然而，以矽穿孔為基礎的三維積體電路(3D ICs)在量產前，有許多挑戰必須被克服，例如：良率、測試、功率、散熱、技術與工具開發等等的挑戰。
在本篇論文，我們提出應用於三維積體電路的記憶體架構的探索以及評估的方法。在本文的第一部分，我們開發了一個針對三維隨機記憶體(3D RAMs)的架構評估與探索的工具。此工具可以評估該三維隨機記憶體的效能、功率、面積、良率以及成本。與現存的工具3DCacti相比，我們更進一步將良率與成本的因素考慮進來。如此一來此工具可以輔助設計者選擇較好的三維架構，進而縮短開發三維隨機記憶體的時間。
在本文的第二部分，我們提出了一個針對三維內容定址記憶體(3D CAMs)的探索與評估得開發工具。內容定址記憶體與隨機記憶體在架構上有些不同。例如：內容定址記憶體有優先權位址編碼器(Priority address encoder, PAE)。首先，我們針對三維內容定址記憶體的架構建立功率、延遲等模型，根據這些模型建立開發工具。如此一來，可以很快速的針對不同三維內容定址記憶體的架構做評估，並提供使用者資訊何種架構比較適合。
散熱在三維積體電路中，是必須要被克服的問題之一。在論文的最後部分，我們提出一個應用於多核心的處理器¬ 記憶體堆疊晶片中，熱感知(Thermal-aware)的記憶體陣列架構。本文中提出兩個熱感知重新對應(remapping)的組態。由實驗結果得知，藉由熱感知重新對應的方法，溫度峰值可以被減少。

摘要(英)

Three-dimensional (3D) integration technology using through-silicon-via (TSV) has been widely acknowledged as one of future integrated circuit (IC) design technologies. 3D integration technology offers many benefits over 2D integration technology, such as high performance, low power, heterogeneous integration, small footprint, etc. However, many challenges should be overcome before volume production of TSV-based 3D ICs become possible, e.g., yield and test challenges, power and thermal challenges, infrastructure challenges, etc.
In this thesis, we propose memory architecture evaluation and exploration methods for 3D ICs. In the first part, an architecture and exploration tools for 3D random access memories (RAMs) is developed. The tool can estimate the performance, power consumption, footprint, yield, and cost for 3D RAMs architectures. Major difference between proposed tool and the existing, 3DCacti, tool is the capability of yield and cost estimation of a 3D RAMs. The designer can get a better 3D architecture which is met his requirement using the proposed tool. This can drastically shorten the design cycle of 3D RAMs.
In the second part, we propose an architecture evaluation and evaluation tool for 3D content addressable memories (CAMs). The CAM is much different from the RAM in architecture. For example, the CAM typical has a priority address encoder (PAE). Models of power, delay, and cost model for 3D CAMs are developed first. Then, the proposed tool can evaluate different 3D CAM architectures such that a better 3D CAM architecture can be obtained easily.
Finally, we propose a thermal-aware memory array architecture to alleviate the thermal problem in multi-core processor-memory stacked chips. Through thermal-aware remapping scheme, the peak temperature can be reduced. Two configuration types for thermal-aware remapping scheme are proposed. Experimental results show that it is possible to find a new configuration such that the peak temperature of the new configuration is lower than that of the original configuration.

關鍵字(中)

★ 三維定址存取記憶體
★ 架構探索與評估
★ 三維積體電路
★ 三維隨機存取記憶體

關鍵字(英)

★ architecture exploration and evaluation
★ 3D CAMs
★ 3D ICs
★ 3D RAMs

論文目次

1 Introduction 1
1.1 Three-Dimensional (3D) Integration Technologies . . . . . . . . . . . . . . . 1
1.2 Challenges for 3D Integration . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Thesis Contribution and Organization . . . . . . . . . . . . . . . . . . . . . 4
2 A Memory Architecture Exploration and Evaluation Tool for 3D RAMs 5
2.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Proposed 3D RAM Architecture . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 3D RAM Design Estimation and Modeling . . . . . . . . . . . . . . . . . . . 8
2.3.1 Overview of Evaluation Flow . . . . . . . . . . . . . . . . . . . . . . 8
2.3.2 TSV Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3.3 Performance, Power, and Footprint Modeling . . . . . . . . . . . . . . 12
2.3.4 Yield and Cost Modeling . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3.5 Architecture Optimization for 3D RAMs . . . . . . . . . . . . . . . . 15
2.4 Evaluation and Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3 Architecture Exploration and Analysis for 3D CAMs 21
3.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2 Typical 2D CAM Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3 Partitioning Strategies for 3D CAM . . . . . . . . . . . . . . . . . . . . . . . 26
3.3.1 Searchline-Partitioned Architecture . . . . . . . . . . . . . . . . . . . 26
3.3.2 Matchline-Partitioned Architecture . . . . . . . . . . . . . . . . . . . 26
3.4 Modeling for 3D CAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.4.1 Matchline Energy for 3D CAM . . . . . . . . . . . . . . . . . . . . . 33
3.4.2 Searchline Energy for 3D CAM . . . . . . . . . . . . . . . . . . . . . 34
3.4.3 Delay Modeling for 3D CAM . . . . . . . . . . . . . . . . . . . . . . 35
3.4.4 PAE Modeling for 3D CAM . . . . . . . . . . . . . . . . . . . . . . . 37
3.5 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.5.1 TSV Cost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.5.2 Effect of Various Configurations on Delay . . . . . . . . . . . . . . . 39
3.5.3 Effect of Various Configurations on Energy . . . . . . . . . . . . . . . 40
3.5.4 Effect of Various Configurations on EDP . . . . . . . . . . . . . . . . 41
3.5.5 Delay and Energy Analysis for PAE . . . . . . . . . . . . . . . . . . . 43
3.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4 Thermal-Aware Memory Array Architecture for Processor-Memory
Stacked 3D ICs 46
4.1 Related Work and Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4.2 Problem Formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.3 Thermal-Aware Memory Design Methodologies . . . . . . . . . . . . . . . . 48
4.3.1 Overview of Thermal-Driven Remapping Scheme . . . . . . . . . . . 48
4.3.2 Reconfigurable Memory Tier Design . . . . . . . . . . . . . . . . . . . 50
4.3.3 Thermal-Aware Remapping Methodology . . . . . . . . . . . . . . . . 51
4.4 Experimental Analysis and Results . . . . . . . . . . . . . . . . . . . . . . . 54
4.4.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.4.2 Thermal Evaluation for Different 3D Systems . . . . . . . . . . . . . 55
4.4.3 Hardware Implementation . . . . . . . . . . . . . . . . . . . . . . . . 60
5 Conclusion and Future Work 63
5.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

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指導教授

李進福(Jin-Fu Li)

審核日期

2010-8-27

推文