鍺奈米線之研製以及高濃度矽鍺氧化機制探討

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：97

、訪客IP：3.15.10.164

姓名

謝維倫(Wei-Lun Hsieh) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

鍺奈米線之研製以及高濃度矽鍺氧化機制探討
(Fabrication of Germanium Nanowire and high concentration SiGe Oxidation Mechanism Study)

相關論文

★ 高效能矽鍺互補型電晶體之研製	★ 高速低功率P型矽鍺金氧半電晶體之研究
★ 應變型矽鍺通道金氧半電晶體之研製	★ 金屬矽化物薄膜與矽/矽鍺界面反應之研究
★ 矽鍺異質源/汲極結構與pn二極體之研製	★ 矽鍺/矽異質接面動態啓始電壓金氧半電晶體之研製
★ 應用於單電子電晶體之矽/鍺量子點研製	★ 矽鍺/矽異質接面動態臨界電壓電晶體及矽鍺源/汲極結構之研製
★ 選擇性氧化複晶矽鍺形成鍺量子點的光特性與光二極體研製	★ 選擇性氧化複晶矽鍺形成鍺量子點及其在金氧半浮點電容之應用
★ 鍺量子點共振穿隧二極體與電晶體之關鍵製程模組開發與元件特性	★ 自對準矽奈米線金氧半場效電晶體之研製
★ 鍺浮點記憶體之研製	★ 利用選擇性氧化單晶矽鍺形成鍺量子點之物性及電性分析
★ 具有自我對準電極鍺量子點單電洞電晶體之製作與物理特性研究	★ 具有自我對準下閘電極鍺量子點單電洞電晶體之研製

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

本論文研究探討以選擇性氧化矽鍺形成鍺量子點與奈米線之關鍵機制，進而提出平面氧化高濃度矽鍺的模型。藉由文獻以及實驗結果的輔助來證實此氧化模型的準確性，並且以此模型來估算形成更高濃度矽鍺層的氧化時間。以此平面氧化高濃度矽鍺模型作為出發點，進而可推導出平面及兩側壁三方向氧化高濃度矽鍺模型。利用電子束微影（electron beam lithography，EBL）以及氮化矽間隙壁的製程，我們實際製作出寬度26 ~ 116 nm的矽鍺奈米線，也觀察到由線轉變成點的過程與鍺濃度及細線的幾何尺寸有其相依關係。另外，由氧化矽鍺線實驗中觀察到，矽鍺細線氧化前的寬度、長度與氧化後所形成量子點位置及大小的關係。也從氧化矽鍺細線的實驗中觀察到高濃度矽鍺經長時間氧化後之情形以及說明矽鍺薄膜氧化時鍺鑽入氮化矽之機制。藉由以上的實驗說明高濃度矽鍺氧化機制，以利後續製作鍺奈米線電晶體以及鍺量子點之應用元件。

摘要(英)

This thesis investigates the key mechanism of forming Ge-QDs or nanowire by the selective oxidaizing SiGe, then brings up the planar oxidation high concentration SiGe model. Through experimental data for assisting the accuracy of this model, we furthermore estimated the required oxidation time for forming higher concentration SiGe layer. Then we derived a three-directional oxidation model for forming high concentration SiGe. In fact, we have made SiGe nanowire width from 26 to 116 nm by EBL and Si3N4 spacer, also observed the transition process of transforming a SiGe wire into Ge-QDs, which are highly dependent on Ge concentration or wire’s geometry. The proposed oxidation model is applicable for fabricating Ge nanowire MOSFET and Ge-QDs application devices in the future.

關鍵字(中)

★ 選擇性氧化矽鍺
★ 奈米線電晶體
★ 鍺奈米線

關鍵字(英)

★ selective oxidation SiGe
★ Ge nanowire
★ nanowire FET

論文目次

第一章簡介.............................................1
1-1 半導體元件發展......................................1
1-2 奈米線電晶體........................................2
1-3 鍺奈米線的優點......................................4
1-4 論文架構............................................5
第二章鍺奈米線製作動機.................................9
2-1 前言................................................9
2-2 氣相-液態-固態機制（VLS機制）形成奈米線.............9
2-3 EBL定義奈米線.....................................11
2-4 選擇性氧化矽鍺形成鍺奈米線.........................12
第三章高濃度矽鍺氧化機制..............................19
3-1 前言...............................................19
3-2 氧化高濃度矽鍺平面模型.........................19
3-3 三維氧化高濃度矽鍺模型.............................22
3-4 鍺的移動與侷限.....................................23
3-4-1 鍺的移動.....................................23
3-4-2 鍺的侷限.....................................25
3-5 過度氧化高濃度矽鍺之情形.......................25
3-6 鍺鑽入氮化矽之機制.............................27
第四章選擇性氧化矽鍺形成鍺奈米線實驗與探討............38
4-1 前言...............................................38
4-2 奈米線尺寸估算.....................................38
4-3 實驗流程...........................................39
4-4 TEM觀測...........................................41
4-5 形成奈米線及量子點之機制.......................42
4-6 總結...........................................43
第五章總結與未來展望..................................52
參考文獻...............................................53
英文簡歷...............................................57

參考文獻

[1] Scott E. Thompson, Mark Armstrong, Chis Auth, Mohsen Alavi, Mark Buehler, Robert Chau, Steve Cea, Tahir Ghani, Glenn Glass, Thomas Hoffman, Chia-Hong Jan, Chis Kenyon, Jason Klaus, Kelly Kuhn, Zhiyong Ma, Brian Mcintyre, Kaizad Mistvy, Anand Murthy, Borna Obradovic, Ramune Nagisetty, Phi Nguyen, Sam Sivakumar, Reaz Shaheed, Lucian Shifren, Bruce Tufts, Sunit Tyagi, Mark Bohr, and Youssef El-Mansy, “A 90-nm logic technology featuring strained-silicon,” IEEE Trans. Electron Devices, vol. 51, p. 1790, 2004.
[2] Robert Chau, Boyan Boyanov, Brian Doyle, Mark Doczy, Suman Datta, Scott Hareland, Ben Jin, Jack Kavalieros, and Matthew Metz, “Silicon nano-transistors for logic applications,” Physica E: Low-dimensional Systems and Nanostructures, vol. 19, p. 1, 2003.
[3] B. Yu, X. H. Sun, G. A. Calebotta, G. R. Dholakia, and M. Meyyappan, “One-dimensional germanium nanowires for future electronics,” J. Clust. Sci., vol. 17, p. 579, 2006.
[4] Tejas Krishnamohan, Donghyun Kim, Chi Dong Nguyen, and Christoph Jungemann, “High-mobility low band-to-band-tunneling strained- germanium double-gate heterostructure FETs: simulations,” IEEE Trans. Electron Devices, vol. 53, p. 1000, 2006.
[5] B. Yu and M. Meyyappan, “Nanotechnology: role in emerging nanoelectronics,” Solid-State Electron., vol. 50, p. 536, 2006.
[6] Krishna Saraswat, Chi On Chui, Tejas Krishnamohan, Donghyun Kim, Ammar Nayfeh, and Abhijit Pethe, “High performance germanium MOSFETs,” Mater. Sci. Eng. B, vol. 135, p. 242, 2006.
[7] Y. Maeda, N. Tsukamoto and Y. Yazawa, “Visible photoluminescence of Ge microcrystals embedded in SiO2 glassy matrices,” Appl. Phys. Lett., vol. 59, p. 3168, 1991.
[8] R. S. Wagner and W. C. Ellis, “Vapor-liquid-solid mechanism of single crystal growth,” Appl. Phys. Lett., vol. 4, p. 89, 1964.
[9] J. R. Heath and F. K. Legcoucs, “A liquid solution synthesis of single-crystal germanium quantum wires,” Chem. Phys. Lett., vol. 208, p. 263, 1993.
[10] Y. Y. Wu and P. D. Yang, “Direct observation of vapor-liquid-solid nanowire growth,” J. Amer. Chem. Soc., vol. 123, p. 3165, 2001.
[11] G. M. Cohen, M. J. Rooks, J. O. Chu, S. E. Laux, P. M. Solomon, J. A. Ott, R. J. Miller, and W. Haensch, “Nanowire metal-oxide-semiconductor field effect transistor with doped epitaxial contacts for source and drain,” Appl. Phys. Lett., vol. 90, p. 233110, 2007.
[12] 吳佳緯，「鍺奈米線與矽奈米線電晶體之研製」，國立中央大學，碩士論文，民國九十八年。
[13] H. K. Liou, P. Mei, U. Gennser, and E. S. Yang, “Effect of Ge concentration on SiGe oxidation behavior,” Appl. Phys. Lett., vol. 59, p. 1200, 1991.
[14] W. T. Lai and P. W. Li, “Growth kinetics and related physical/electrical properties of Ge quantum dots formed by thermal oxidation of Si1-xGex-on-insulator,” Nanotechnol., vol. 18, p. 145402, 2007.
[15] Cao M., Wang A., and Saraswat KC, “Low Pressure Chemical Vapor Deposition of Si1-xGex Films on SiO2 Characterization and Modeling,” Journal of the electrochemical society, vol. 142, p. 1566-1572, 1995.
[16] Rodriguez A., Ortiz MI, Sangrador J., Rodrihuez T., Avella M., Prieto A. C., Terres A., Jimenez J., Kling A., and Ballesteros C., ”Comparative study of the luminescence of structures with Ge nanocrystals formed by dry and wet oxidation of SiGe films,” Nanotechnol. vol. 18, p. 065702, 2007.
[17] P. W. Li, W. M. Liao, and S. W. Lin, “Formation of atomic-scale germanium quantum dots by selective oxidation of SiGe/Si-on-insulator,” Appl. Phys. Lett., vol. 83, p. 4628, 2003.
[18] Ma XB., Liu WL., Chen C., Du XF., Liu XY., Song ZH., and Lin CL., ”Fabrication of high Ge content SiGe-on-insulator with low dislocation density by modified Ge condensation,” Applied Surface Science, vol. 255, p. 7743-7748, 2007.
[19] Balakumar S., Peng S., Hoe KM, A. Agarwal, G. Q. Lo, R. Kumar, N. Balasubramanian, D. L. Kwong, and S. Tripathy, “SiGeO layer formation mechanism at the SiGe/oxide interfaces during Ge condensation,” Appl. Phys. Lett., vol. 90, p. 032111, 2007.
[20] 曾柏皓，「鍺量子點嵌入氮化矽/二氧化矽/氮化矽層之浮點電晶體研製」，國立中央大學，碩士論文，民國九十九年。
[21] James D. Plummer, Michael D. Deal, and Peter B. Griffin, “Silicon VLSI Technology：Fundamental, Practice and Modeling,” CH6, p. 317-319, 2005.
[22] Kim SY, Lee HJ, and Ko DH, “Agglomeration of Cylindrically Condensed Cores in Si1-xGex Nanowires by Oxidation,” Electrochemical and Solid State Letters, vol. 13, p. K57-K9, 2010.
[23] 陳柏翰，「高鍺濃度薄膜實驗」，國立中央大學，碩士班，民國九十九年。
[24] Y. R. Chang, C.Y. Chien, S. W. Lee, and P. W. Li, “Influence of host dielectrics on the formation of Ge quantum dots/wires in silicon oxide and silicon nitride matrices and associated optical and thermal properties,” unpublished.

指導教授

李佩雯(Pei-Wen Li)

審核日期

2010-10-27

推文