以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：158

、訪客IP：18.119.111.9

姓名	曾子維(Tsu-Wei Tseng)  查詢紙本館藏	畢業系所	電機工程學系
論文名稱	記憶體內建自我修復技術與設計自動化 (Memory Built-In Self-Repair Techniques and Design Automation)
相關論文	★ 應用於三元內容定址記憶體之低功率設計與測試技術 ★ 用於隨機存取記憶體的接線驗證演算法 ★ 用於降低系統晶片內測試資料之基礎矽智產 ★ 內容定址記憶體之鄰近區域樣型敏感瑕疵測試演算法 ★ 內嵌式記憶體中位址及資料匯流排之串音瑕疵測試 ★ 用於系統晶片中單埠與多埠記憶體之自我修復技術 ★ 用於修復嵌入式記憶體之基礎矽智產 ★ 自我修復記憶體之備份分析評估與驗證平台 ★ 使用雙倍疊乘累加命中線之低功率三元內容定址記憶體設計 ★ 可自我測試且具成本效益之記憶體式快速傅利葉轉換處理器設計 ★ 低功率與可自我修復之三元內容定址記憶體設計 ★ 多核心系統晶片之診斷方法 ★ 應用於網路晶片上隨機存取記憶體測試及修復之基礎矽智產 ★ 應用於貪睡靜態記憶體之有效診斷與修復技術 ★ 應用於內嵌式記憶體之高效率診斷性資料壓縮與可測性方案 ★ 應用於隨機存取記憶體之有效良率及可靠度提升技術
檔案	[Endnote RIS 格式]    [Bibtex 格式]    [相關文章]   [文章引用]   [完整記錄]   [館藏目錄]   [檢視]  [下載] 本電子論文使用權限為同意立即開放。 已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。 請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。
摘要(中)	嵌入式記憶體式系統晶片(system-on-chip, SOC)設計中之重要元件。含有數百個記憶體之系統晶片已不再陌生。此外，這些記憶體通常佔據整體系統晶片之大量面積，造成記憶體良率支配整體系統晶片之良率。因此，有效提升系統晶片中記憶體良率之技術是需要的。而記憶體內建自我修復技術(memory built-in self-repair, BISR)已被廣泛使用於提升記憶體良率。 論文的第一部分，針對多埠記憶體(multi-port RAMs)提出一瑕疵-覺知式記憶體自我修復(defect-aware BISR, DABISR)方法，可藉由定位出埠間瑕疵(inter-port defects)位置來提升多埠記憶體之修復效率。並且，我們提出了針對記憶體中字組線(word-line)間與位元線(bit-line)間埠間瑕疵定位之瑕疵定位演算法(defect-location algorithm, DLA)。DLA所存取的位址空間非常小。實驗結果顯示，所提出的瑕疵定位演算法，在20%埠間瑕疵機率假設下，對一雙埠記憶體可提升8.4%-14.4%之修復率。 論文第二部分，提出兩種分享式BISR方法，用以降低BISR於系統晶片中的面積成本。所提出的循序-分享式BISR可循序的修復多記憶體模組。其中，廣域端之備份元件分析器(redundancy analyzer)可負責待測記憶體之備份元件分析。與特定式BISR(i.e., 每一記憶體配置一獨立的BISR系統)電路比較，在四個不同尺寸記憶體的假設下，所提出之循序-分享式BISR可達成約40%-50%的節省面積比例。而為了減少面積成本且不造成長測試時間，我們也提出一平行-分享式BISR方法，可平行修復多記憶體模組。其中，廣域端之備份元件分析器可以分時多工(time multiplexing)之方式執行多記憶體模組之備份元件分析。實驗結果顯示，所提出之平行-分享式BISR之測試時間，極度接近特定式(dedicated)BISR之測試時間。然而，在五記憶體的假設下與特定式BISR比較，所提出之平行-分享式BISR可有約20%之節省面積比例。 論文第三部分，提出一記憶體BISR之設計自動化基礎框架(BISR design automation framework)，可針對系統晶片中之多記憶體模組，規劃與自動產生BISR電路。所提出之BISR設計自動化基礎框架可在最大繞線之限制下，決定不同記憶體模組使用循序-分享式BISR或平行-分享式BISR電路，並且最小化整體BISR電路之面積與測試時間成本。此外，BISR相關設計參數可被最佳化使得BISR之面積成本可進一步降低。實驗結果顯示，針對50個記憶體模組，在不同功率消耗限制與最大繞線距離限制下與特定式BISR比較，所提出之BISR設計自動化基礎框架可達到約20.96%-33.67%之節省面積比例。
摘要(英)	Embedded random access memory (RAM) is one key component in modern system-on-chip (SOC) designs. Several hundreds of RAM cores in a complex SOC is common. Furthermore, these RAM cores usually represent more than one half of the area of the SOC. Therefore, the yield of RAM cores dominates the yield of modern SOCs. Effective yield-enhancement techniques thus are needed for RAM cores in an SOC. Built-in self-repair (BISR) techniques are widely used to enhance the yield of embedded RAMs. In the first part of this thesis, a defect-aware BISR (DABISR) scheme is proposed to improve the repair efficiency of multi-port RAMs (MPRAMs) by enhancing the location capability of inter-port faults caused by inter-port defects. Also, two defect-location algorithms (DLAs) are proposed to locate the inter-port defects between word-lines and bit-lines with a small range of the address space. Thus, the time complexity for executing the proposed DLAs is low. Experimental results show that the proposed defect-location algorithms can help to gain 8.4%−14.4% increase of repair rate for different redundancy configurations for a faulty two-port RAM with 20% inter-port faults. In the second part of this thesis, two shared BISR schemes are proposed to reduce the area cost of BISR circuits in an SOC. A shared-serial BISR scheme is proposed to repair multiple RAMs sequentially. A global redundancy analyzer is responsible for performing the redundancy analysis for the RAMs under repair. In comparison with the dedicated BISR scheme, i.e., each RAM is equipped with a self-contained BISR circuit, the proposed shared-serial BISR scheme can achieve about 40%−50% ratio of the area reduction for four RAMs. To reduce the area cost without incurring long test time, a shared-parallel BISR scheme also is proposed to test and repair multiple RAMs in parallel. The shared-parallel BISR scheme consists of a global BIRA which serves multiple RAMs in time-multiplexing method. Experimental results show that the test and repair time of the shared-parallel BISR scheme approximates to that of the dedicated BISR scheme. Also, the shared-parallel BISR scheme can achieve about 20% area reduction compared with the dedicated BISR circuits for five RAMs. In the third part of this thesis, a memory BISR design automation framework is proposed to plan and generate BISR circuits for RAMs in an SOC. The design automation framework can select the RAMs which can share a shared-serial or a shared-parallel BISR circuit under the routing distance and test power constraint, such that the number of required BISR circuits and the test time is minimized. Furthermore, design parameters of a BISR circuit can be optimized through the design automation framework such that the area cost of the BISR circuits in an SOC can be reduced further. Experimental results show that the BISR circuits generated by the proposed automation framework can save about 20.96%−33.67% area cost compared with the dedicated BISR circuits for 50 RAMs with respect to different test power constraints and distance constraints (i.e., maximum routing distance between the RAMs and the BISR circuit).
關鍵字(中)	★ 記憶體修復 ★ 記憶體測試	關鍵字(英)	★ yield enhancement ★ redundancy ★ memory repair ★ memory test
論文目次	1 Introduction 1 1.1 Memory Built-In Self-Repair Techniques . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Existing Memory BISR Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.3 Challenges of Memory BISR Design in SOCs . . . . . . . . . . . . . . . . . . . . 13 1.3.1 Fault-Location Problem of Typical Tests for Multi-Port RAMs . . . . . . . 14 1.3.2 Shared BISR Techniques for RAMs . . . . . . . . . . . . . . . . . . . . . 15 1.3.3 BISR Planning for RAMs in SOCs . . . . . . . . . . . . . . . . . . . . . . 17 1.4 Thesis Motivations and Contributions . . . . . . . . . . . . . . . . . . . . . . . . 20 1.5 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2 A Defect-Aware BISR Scheme for Multi-Port RAMs 26 2.1 Fault-Location Ability of Typical Memory Test Algorithms . . . . . . . . . . . . . 27 2.2 Proposed Defect-Aware BISR Scheme . . . . . . . . . . . . . . . . . . . . . . . . 30 2.2.1 Block Diagram of BISR . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.2.2 Redundancy Analysis Algorithm . . . . . . . . . . . . . . . . . . . . . . . 31 2.3 Defect-Location Algorithms for Locating Bridge Defects betweenWord-lines/Bitlines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.3.1 Location of Bridge Defects between Word-Lines . . . . . . . . . . . . . . 32 2.3.2 Location of Bridge Defects between Bit-Lines . . . . . . . . . . . . . . . 34 2.3.3 Discussions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.4 Design of DABISR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.4.1 Design of Wrapper for MPRAMs . . . . . . . . . . . . . . . . . . . . . . 37 2.4.2 Design of BIRA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.5 Analysis and Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.5.1 Analysis of Repair Efficiency . . . . . . . . . . . . . . . . . . . . . . . . 40 2.5.2 Analysis of Test Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.5.3 Analysis of Area Cost . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3 Shared BISR Schemes for RAMs in SOCs 47 3.1 Shared-Serial BISR Scheme for Low Area Cost . . . . . . . . . . . . . . . . . . . 48 3.1.1 Architecture of the Shared-Serial BISR Scheme . . . . . . . . . . . . . . . 48 3.1.2 Design of the ReBIRA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.1.3 Extended Shared-Serial BISR for Supporting Single-Port and Multi-Port RAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.1.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.2 Shared-Parallel BISR Scheme for Low Test Time . . . . . . . . . . . . . . . . . . 56 3.2.1 Overview of the Proposed Shared Parallel BISR . . . . . . . . . . . . . . . 57 3.2.2 Design of the Shared Parallel BISR Scheme . . . . . . . . . . . . . . . . . 59 3.2.3 Experimental Results and Analysis . . . . . . . . . . . . . . . . . . . . . 66 3.3 Chip-Level Controlling Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 3.4 Adaptively Reconfigurable Fusing Methodology for Memory BISR . . . . . . . . 79 3.4.1 Typical Fusing Methodology . . . . . . . . . . . . . . . . . . . . . . . . . 79 3.4.2 Adaptively Reconfigurable Fusing Methodology . . . . . . . . . . . . . . 81 3.4.3 Analysis of Repair Signature Loading Time . . . . . . . . . . . . . . . . . 82 3.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4 Memory BISR Design Automation Framework 87 4.1 Proposed BISR Automation Framework . . . . . . . . . . . . . . . . . . . . . . . 88 4.2 Memory Grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 4.3 Simulation of Redundancy Configurations . . . . . . . . . . . . . . . . . . . . . . 94 4.3.1 Simulation of Redundancy Configurations of RAMs for the Yield Maximizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 4.3.2 Simulation of Redundancy Configurations of RAMs for Minimizing Yield Degradation under AC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 4.4 BISR Scheme Allocation and Bitmap Sizing . . . . . . . . . . . . . . . . . . . . . 108 4.4.1 BISR Scheme Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 4.4.2 Bitmap Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 4.5 Experimental Results and Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . 114 5 Conclusions and FutureWork 125
參考文獻	[1] T.-W. Tseng, J.-F. Li, and C.-C. Hsu, “ReBISR: a reconfigurable built-in self-repair scheme for random access memories in SOCs,” IEEE Trans. on VLSI Systems, vol. 18, no. 6, pp. 921–932, Jun.2010. [2] T.-W. Tseng, J.-F. Li, and D.-M. Chang, “A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmap,” in Proc. IEEE/ACM Design, Automation, and Test in Europe(DATE), Mar 2006, pp. 53–58. [3] V. Schober, S. Paul, and O. Picot, “Memory built-in self-repair using redundant words,” in Proc. IEEE Int’l Test Conf. (ITC), Oct. 2001, pp. 995–1001. [4] C.-W. Wang, C.-F. Wu, J.-F. Li, C.-W. Wu, T. Teng, K. Chiu, and H.-P. Lin, “A built-in self-test and self-diagnosis scheme for embedded SRAM,” in Proc. Ninth Proc. IEEE Asian Test Symp. (ATS),Taipei, Dec. 2000, pp. 45–50. [5] C.-T. Huang, C.-F. Wu, J.-F. Li, and C.-W. Wu, “Built-in redundancy analysis for memory yield improvement,” IEEE Trans. on Reliability, vol. 52, no. 4, pp. 386–399, Dec. 2003. [6] C.-L. Su, R.-F. Huang, and C.-W. Wu, “A processor-based built-in self-repair design for embedded memories,” in Proc. IEEE Asian Test Symp. (ATS), Nov. 2003, pp. 366–371. [7] C.-D. Huang, T.-W. Tseng, and J.-F. Li, “An infrastructure IP for repairing multiple RAMs in SOCs,” in Proc. IEEE Int. Symp. VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2006, pp. 163–166. [8] T.-W. Tseng, C.-S. Hou, and J.-F. Li, “Automatic generation of memory built-in self-repair circuits in SOCs for minimizing test time and area cost,” in Proc. IEEE VLSI Test Symp. (VTS), April 2010, pp. 21–26. [9] C.-S. Hou and J.-F. Li, “Test and repair scheduling for built-in self repair RAMs in SOCs,” in Proc. IEEE Int’l Symp. on Electronic Design, Test & Applications (DELTA), Jan. 2010, pp. 3–7. [10] I. Parulkar, S. Anandakumar, G. Agarwal, G. Liu, K. Rajan, and F. Chiu, “DFX of a 3rd generation, 16-core/32-thread UltraSPARCTM CMT microprocessor,” in Proc. IEEE Int’l Test Conf. (ITC), Oct.2008, pp. 1–10. [11] S. Hamdioui, G. Gaydadjiev, and A. van de Goor, “The state-of-art and future trends in testing embedded memories,” in Proc. IEEE Int’l Workshop on Memory Technology, Design and Testing (MTDT), Aug. 2004, pp. 54–59. [12] I. Kim, Y. Zorian, G. Komoriya, H. Pham, F. P. Higgins, and J. L. Lweandowski, “Built in self repair for embedded high density SRAM,” in Proc. IEEE Int’l Test Conf. (ITC), Oct. 1998, pp. 1112–1119. [13] R. Rajsuman, “Design and test of large embedded memories: an overview,” IEEE Design & Test of Computers, vol. 18, no. 3, pp. 16–27, May 2001. [14] Y. Zorian, “Embedded memory test & repair: Infrastructure IP for SOC yield,” in Proc. IEEE Int’l Test Conf. (ITC), Oct. 2002, pp. 340–349. [15] Y. Zorian and S. Shoukourian, “Embedded-memory test and repair: Infrastructure IP for SoC yield,” IEEE Design & Test of Computers, vol. 20, pp. 58–66, May-June 2003. [16] S. Nakahara, K. Higeta, M. Kohno, T. Kawamura, and K. Kakitani, “Built-in self-test for GHz embedded SRAMs using flexible pattern generator and new repair algorithm,” in Proc. IEEE Int’l Test Conf. (ITC), Sept. 1999, pp. 301–310. [17] D. K. Bhavsar, “An algorithm for row-column self-repair of RAMs and its implementation in the Alpha 21264,” in Proc. IEEE Int’l Test Conf. (ITC), Sept. 1999, pp. 311–318. [18] T. Kawagoe, J. Ohtani, M. Niiro, T. Ooishi, M. Hamada, and H. Hidaka, “A built-in self-repair analyzer (CRESTA) for embedded DRAMs,” in Proc. IEEE Int’l Test Conf. (ITC), 2000, pp. 567–574. [19] D. Xiaogang, S. M. Reddy, W.-T. Cheng, J. Rayhawk, and N. Mukherjee, “At-speed built-in self-repair analyzer for embedded word-oriented memories,” in Proc. International Conference on VLSI Design, 2004, pp. 895–900. [20] P. Ohler, Hellebrand, Sybille, Wunderlich, and Hans-Joachim, “An integrated built-in test and repair approach for memories with 2D redundancy,” in Proc. IEEE European Test Symp. (ETS), May 2007, pp. 91–96. [21] M. Nicolaidis, N. Achouri, and S. Boutobza, “Optimal reconfiguration functions for column or data bit built-in self-repair,” in Proc. IEEE/ACM Design, Automation, and Test in Europe (DATE), Mar.2003, pp. 590–595. [22] ——, “Dynamic data-bit memory built-in self-repair,” in Proc. IEEE/ACM Int’l Conf. on Computer-Aided Design (ICCAD), Nov. 2003, pp. 588–594. [23] ——, “A memory built-in self-repair for high defect densities based on error polarities,” in Proc.IEEE Int’l Symp. on Defect and Fault Tolerance in VLSI Systems (DFT), Nov. 2003, pp. 456–466. [24] C.-L. Su, Y.-T. Yeh, and C.-W. Wu, “An integrated ECC and redundancy repair scheme for memory reliability enhancement,” in Proc. IEEE Int’l Symp. on Defect and Fault Tolerance in VLSI Systems (DFT), Oct. 2005, pp. 81–89. [25] S.-K. Lu, Y.-C. Tsai, C.-H. Hsu, K.-H. Wang, and C.-W. Wu, “Efficient built-in redundancy analysis for embedded memories with 2-D redundancy,” IEEE Trans. on VLSI Systems, vol. 14, no. 1, pp.34–42, Jan. 2006. [26] J.-F. Li, J.-C. Yeh, R.-F. Huang, and C.-W. Wu, “A built-in self-repair design for RAMs with 2-D redundancy,” IEEE Trans. on VLSI Systems, vol. 13, no. 6, pp. 742–745, June 2005. [27] T.-W. Tseng, J.-F. Li, C.-C. Hsu, A. Pao, K. Chiu, and E. Chen, “A reconfigurable built-in self-repair scheme for multiple repairable RAMs in SOCs,” in Proc. IEEE Int’l Test Conf. (ITC), Oct 2006, Paper 30.2, pp. 1–8. [28] T.-W. Tseng, C.-H. Wu, Y.-J. Huang, J.-F. Li, A. Pao, K. Chiu, and E. Chen, “A built-in self-repair scheme for multiport RAMs,” in Proc. IEEE VLSI Test Symp. (VTS), May 2007, pp. 355–360. [29] C.-D. Huang, J.-F. Li, and T.-W. Tseng, “ProTaR: an infrastructure IP for repairing RAMs in SOCs,” IEEE Trans. on VLSI Systems, vol. 15, no. 10, pp. 1135–1143, Oct. 2007. [30] T.-W. Tseng and J.-F. Li, “A shared parallel built-in self-repair scheme for random access memories in SOCs,” in Proc. IEEE Int’l Test Conf. (ITC), Oct. 2008, pp. 1–9. [31] A. Benso, S. Chiusano, G. D. Natale, and P. Prinetto, “An on-line BIST RAM architecture with self-repair capabilities,” IEEE Trans. on Reliability, vol. 51, no. 1, pp. 123–128, Mar. 2002. [32] S.-K. Thakur, R.-A. Parekhji, and A.-N. Chandorkar, “On-chip test and repair of memories for static and dynamic faults,” in Proc. IEEE Int’l Test Conf. (ITC), Oct. 2006, pp. 1–10. [33] W. Jeong, I. Kang, K. Jin, and S. Kang, “A fast built-in redundancy analysis for memories with optimal repair rate using a line-based search tree,” IEEE Trans. on VLSI Systems, vol. 17, no. 12, pp.1665–1678, Dec. 2009. [34] A. Tanabe, T. Takeshima, H. Koike, Y. Aimoto, M. Takada, T. Ishijima, N. Kasai, H. Hada, K. Shibahara, T. Kunio, T. Tanigawa, T. Saeki, M. Sakao, H. Miyamoto, H. Nozue, S. Ohya, T. Murotani, K. Koyama, and T. Okuda, “A 30-ns 64-Mb DRAM with built-in self-test and self-repair function,” IEEE Jour. of Solid-State Circuits, vol. 27, no. 11, pp. 1525–1533, Nov. 1992. [35] P. Mazumder and Y.-S. Jih, “A new built-in self-repair approach to VLSI memory yield enhancement by using neural-type circuits,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, no. 1, pp. 124–136, Jan. 1993. [36] O. Wada, T. Namekawa, H. Ito, A. Nakayama, and S. Fujii, “Post-packaging auto repair techniques for fast row cycle embedded dram,” in Proc. IEEE Int’l Test Conf. (ITC), Oct. 2004, pp. 1016–1023. [37] S.-K. Lu, C.-L. Yang, Y.-C. Hsian, and C.-W. Wu, “Efficient BISR techniques for embedded memories considering cluster faults,” IEEE Trans. on VLSI Systems, vol. 18, no. 2, pp. 184–193, Feb. 2010. [38] I. Kang, W. Jeong, and S. Kang, “High-efficiency memory BISR with two serial RA stages using spare memories,” Electronic Letters, vol. 44, no. 8, pp. 515–517, April 2008. [39] H.-N. Liu, Y.-J. Huang, and J.-F. Li, “A built-in self-repair method for RAMs in mesh-based NoCs,” in Proc. IEEE Int’l Symp. on VLSI Design, Automation and Test (VLSI-DAT), April 2009, pp. 259–262. [40] Z.-Y. Wang, Y.-M. Tsai, and S.-K. Lu, “Built-in self-repair techniques for heterogeneous memory cores,” in IEEE Int’l Symp. on Dependable Computing, Nov. 2009, pp. 69–74. [41] M. Rab, A.A.Bawa, and N. Touba, “Improving memory repair by selective row partitioning,” in Proc. IEEE Int’l Symp. on Defect and Fault Tolerance in VLSI Systems (DFT), Oct. 2009, pp. 211–219. [42] J. R. Day, “A fault-driven, comprehensive redundancy algorithm,” in IEEE Design & Test of Computers, vol. 2, June 1985, pp. 35–44. [43] S.-Y. Kuo and W. K. Fuchs, “Efficient spare allocation in reconfigurable arrays,” IEEE Design & Test of Computers, vol. 4, no. 1, pp. 24–31, Feb. 1987. [44] C.-L. Wey and F. Lombardi, “On the repair of redundant RAM’s,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 6, no. 3, pp. 222–231, Mar. 1987. [45] W.-K. Huang, Y.-N. Shen, and F. Lombardi, “New approaches for the repair of memories with redundancy by row/column deletion for yield enhancement,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 9, no. 3, pp. 323–328, Mar. 1990. [46] R. Libeskind-Hadas and C. Liu, “Fast search algorithms for reconfiguration problems,” in Proc. IEEE Int’l Symp. on Defect and Fault Tolerance in VLSI Systems (DFT), Nov. 1991, pp. 260–273. [47] Y. Han, J. Suh, and C. Lee, “Redundancy analysis simulation for electrical die sorting (EDS) process,” in Proc. IEEE Int’l Conf. on Parallel and Distributed Computing, Applications and Technologies, Aug. 2003, pp. 757–761. [48] M. Tarr, D. Boudreau, and R. Murphy, “Defect analysis system speeds test and repair of redundant memories,” Electronics, pp. 175–179, Jan. 12 1984. [49] Y. Nagura, M. Mullins, A. Sauvageau, Y. Fujiwara, K. Furue, R. Ohmura, T. Komoike, T. Okitaka, T. Tanizaki, K. Dosaka, K. Arimito, Y. Koda, and T. Tada, “Test cost reduction by at-speed BISR for embedded DRAMs,” in Proc. IEEE Int’l Test Conf. (ITC), Oct. 2001, pp. 182–187. [50] Y. Zorian, “Yield improvement and repair trade-off for large embedded memories,” in Proc. IEEE/ACM Design, Automation, and Test in Europe (DATE), 2000, pp. 69–70. [51] R. McConnell and R. Rajsuman, “Test and repair of large embedded DRAMs: Part 1,” in Proc. IEEE Int’l Test Conf. (ITC), 2002, pp. 163–172. [52] C.-T. Huang, J.-R. Huang, C.-F. Wu, C.-W. Wu, and T.-Y. Chang, “A programmable BIST core for embedded DRAM,” IEEE Design & Test of Computers, vol. 16, no. 1, pp. 59–70, Jan.-Mar. 1999. [53] C. Cheng, C.-T. Huang, J.-R. Huang, C.-W. Wu, C.-J. Wey, and M.-C. Tsai, “BRAINS: A BIST complier for embedded memories,” in Proc. IEEE Int’l Symp. on Defect and Fault Tolerance in VLSI Systems (DFT), Yamanashi, Oct. 2000, pp. 299–307. [54] A. J. van de Goor, “Using march tests to test SRAMs,” IEEE Design & Test of Computers, vol. 10, no. 1, pp. 8–14, Mar. 1993. [55] T.-W. Tseng, Y.-J. Huang, and J.-F. Li, “DABISR: a defect-aware built-in self-repair scheme for single/multi-port RAMs in SOCs,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 10, pp. 1628–1639, Sept. 2010. [56] T.-W. Tseng and J.-F. Li, “A built-in method to repair SoC RAMs in parallel,” IEEE Design & Test of Computers, Aug. 2010 (accepted). [57] J.-F. Li, T.-W. Tseng, and C.-S. Hou, “Reliability-enhancement and self-repair schemes for RAMs with static and dynamic faults,” IEEE Trans. on VLSI Systems, vol. 18, no. 9, pp. 1361–1366, Sept. 2010. [58] R. Zappa, C. Selva, D. Rimondi, C. Torelli, M. Crestan, G. Mastrodomenico, and L. Albani, “Micro programmable built-in self repair for SRAMs,” in Proc. IEEE Int’l Workshop on Memory Technology, Design and Testing (MTDT), Aug. 2004, pp. 72–77. [59] S.-K. Lu and S.-C. Huang, “Built-in self-test and repair (BISTR) techniques for embedded rams,” in Proc. IEEE Int’l Workshop on Memory Technology, Design and Testing (MTDT), Aug. 2004, pp. 60–64. [60] M. Nicolaidis, N. Achouri, and L. Anghel, “A diversified memory built-in self-repair approach for nanotechnologies,” in Proc. IEEE VLSI Test Symp. (VTS), Apr. 2004, pp. 313–318. [61] K. Chakraborty, S. Kulkami, M. Bhattacharya, P. Mazumder, and A. Gupta, “A physical design tool for built-in self-repairable RAMs,” IEEE Trans. on VLSI Systems, vol. 9, no. 2, pp. 352–364, April 2001. [62] S.-K. Lu and C.-H. Hsu, “Built-in self-repair for divided word line memory,” in Proc. IEEE Int’l Symp. on Circuits and Systems (ISCAS), 2001, pp. 13–16. [63] S.-K. Lu, “Built-in self-repair techniques for embedded RAMs,” IET Proc. Computers and Digital Technqiues, vol. 150, no. 4, pp. 201–208, July 2003. [64] M. Nicolaidis, N. Achouri, and L. Anghel, “Memory built-in self-repair for nanotechnologies,” in Proc. IEEE Int’l Symp. on On-Line Testing (IOLTS), July 2003, pp. 94–98. [65] K. Pekmestzi, N. Axelos, I. Sideris, and N. Moshopoulos, “A BISR architecture for embedded memories,” in Proc. IEEE Int’l Symp. on On-Line Testing (IOLTS), July 2008, pp. 149–154. [66] A. Sehgal, A. Dubey, E. Marinissen, C. Wouters, H. Vranken, and K. Chakrabarty, “Yield analysis for repairable embedded memories,” in IEEE European Test Workshop (ETW), May 2003, pp. 35–40. [67] J.-F. Li, J.-C. Yeh, R.-F. Huang, C.-W. Wu, P.-Y. Tsai, A. Hsu, and E. Chow, “A built-in self-repair scheme for semiconductor memories with 2-D redundancy,” in Proc. IEEE Int’l Test Conf. (ITC), Sept. 2003, pp. 393–402. [68] S.-K. Lu, Y.-C. Tsai, and S.-C. Huang, “A BIRA algorithm for embedded memories with 2D redundancy,” in Proc. IEEE Int’l Workshop on Memory Technology, Design and Testing (MTDT), Aug. 2005, pp. 121–126. [69] T.-W. Tseng and J.-F. Li, “A low-cost built-in redundancy-analysis scheme for word-oriented RAMs,” IEEE Trans. on VLSI Systems, July 2010 (accepted). [70] Y.-J. Huang, D.-M. Chang, and J.-F. Li, “A built-in redundancy-analysis scheme for self-repairable RAMs with two-level redundancy,” in IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems (DFT), Oct 2006, pp. 362–370. [71] S.-K. Lu, C.-L. Yang, and H.-W. Lin, “Efficient BISR techniques for word-oriented embedded memories with hierarchical redundancy,” in Proc. IEEE Int’l Conf. on Computer and Information Science, July 2006, pp. 355–360. [72] D.-M. Chang, J.-F. Li, and Y.-J. Huang, “A built-in redundancy-analysis scheme for random access memories with two-level redundancy,” J. Electronic Testing: Theory and Application, vol. 24, no. 1, pp. 181–192, Jan. 2008. [73] A. Sehgal, E. J. Marinissen, C.Wouters, H. Vranken, and K. Chakrabarty, “Redundancy modeling and array yield analysis for repairable embedded memories,” IEE Proc. Computer and Digital Techniques, vol. 152, no. 1, pp. 97–106, Jan. 2005. [74] W. Jeong, T. Han, and S. Kang, “An advanced BIRA using parallel sub-analyzers for embedded memories,” in Proc. IEEE International SOC Conference (ISOCC), Nov. 2009, pp. 249–252. [75] W. Jeong, K. Park, and S. Kang, “An area-efficient built-in redundancy analysis for embedded memories with optimal repair rate using 2-D redundancy,” in Proc. IEEE International SOC Conference (ISOCC), Nov. 2009, pp. 353–356. [76] J. Ohtani, T. Ooishi, T. Kawagoe, M. Niiro, M. Maruta, and H. Hidaka, “A shared built-in self-repair analysis for multiple embedded memories,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), vol. 4, 2001, pp. 187–190. [77] R.-F. Huang, C.-L. Su, C.-W. Wu, S.-T. Lin, K.-L. Luo, and Y.-J. Chang, “Fail pattern identification for memory built-in self-repair,” in Proc. IEEE Asian Test Symp. (ATS), Nov. 2004, pp. 366–371. [78] W. Xiaopeng, J. Mehler, F. Meyer, and P. Nohpill, “Memory yield and complexity of built-in selfrepair,” in Proc. IEEE Int’l Symp. on Reliability and Maintainability, Jan. 2005, pp. 238–244. [79] C.-W. Wang, K.-L. Cheng, C.-T. Huang, and C.-W. Wu, “Test and diagnosis of word-oriented multiport memories,” in Proc. IEEE VLSI Test Symp. (VTS), Apr. 2003, pp. 248–253. [80] R. C. Aitken, “A modular wrapper enabling high speed BIST and repair for small wide memories,” in Proc. IEEE Int’l Test Conf. (ITC), Oct. 2004, pp. 997–1005. [81] C.-W. Wang, J.-R. Huang, Y.-F. Lin, K.-L. Cheng, C.-T. Huang, C.-W. Wu, and Y.-L. Lin, “Test scheduling of BISTed memory cores for SOC,” in Proc. IEEE Asian Test Symp. (ATS), Nov. 2002, pp. 356–361. [82] M. Miyazaki, T. Yoneda, and H. Fujiwara, “A memory grouping method for sharing memory BIST logic,” in Proc. IEEE Asia South Pacific Design Automation Conference (ASP-DAC), Jan. 2006, pp. 671–676. [83] T. Yoneda, Y. Fukuda, and H. Fujiwara, “Test scheduling for memory cores with built-in self-repair,” in Proc. IEEE Asian Test Symp. (ATS), Oct. 2007, pp. 199–204. [84] Q. Xu, B. Wang, A. Ivanov, and F. Y. Young, “Testing scheduling for built-in self-tested embedded SRAMs with data retention faults,” IET Proc. Computers and Digital Techniques, vol. 1, no. 3, pp. 256–264, May 2007. [85] H. Melzner and A. Olbrich, “Maximization of good chips per wafer by optimization of memory redundancy,” IEEE Trans. on VLSI Systems, vol. 20, no. 2, pp. 68–76, May 2007. [86] J. P. Bickford, R. Rosner, E. Hedberg, J. W. Yoder, and T. S. Barnett, “SRAM redundancy – silicon area versus number of repairs trade-off,” in IEEE Int’l Conf. on Advanced Semiconductor Manufacturing, May 2008, pp. 387–392. [87] J. Cha and S. Gupta, “Characterization of granularity and redundancy for SRAMs for optimal yield per-area,” in Proc. IEEE Int’l Conf. on Computer Design (ICCD), 2008, pp. 219–226. [88] R.-F. Huang, J.-F. Li, J.-C. Yeh, and C.-W. Wu, “RAISIN: A tool for evaluating redundancy analysis schemes in reparable embedded memories,” IEEE Design & Test of Computers, vol. 24, no. 4, pp. 386–396, Aug. 2007. [89] S. Hamdioui, A. J. van de Goor, D. Eastwick, and M. Rodgers, “Realistic fault models and test procedure for multi-port SRAMs,” in Proc. IEEE Int’l Workshop on Memory Technology, Design and Testing (MTDT), Aug. 2001, pp. 65–72. [90] A. J. van de Goor and I. Schanstra, “Address and data scrambling: causes and impact on memory tests,” in Proc. IEEE Int’l Workshop on Electronic Design, Test, and Applications (DELTA), Jan. 2002, pp. 128–136. [91] J. Zhao, S. Irrinki, M. Puri, and F. Lombardi, “Detection of inter-port faults in multi-port static RAMs,” in Proc. IEEE VLSI Test Symp. (VTS), Apr. 2000, pp. 297–302. [92] C.-F. Wu, C.-T. Huang, K.-L. Cheng, C.-W. Wang, and C.-W. Wu, “Simulation-based test algorithm generation and port scheduling for multi-port memories,” in Proc. IEEE/ACM Design Automation Conf. (DAC), June 2001, pp. 301–306. [93] R.-F. Huang, J.-F. Li, J.-C. Yeh, and C.-W. Wu, “A simulator for evaluating redundancy analysis algorithms of repairable embedded memories,” in Proc. IEEE Int’l Workshop on Memory Technology, Design and Testing (MTDT), July 2002, pp. 68–73. [94] S. Bahl, “A sharable built-in self-repair scheme for semiconductor memories with 2-D redundancy scheme,” in Proc. IEEE Int’l Symp. on Defect and Fault Tolerance in VLSI Systems (DFT), 2007, pp. 331–339. [95] C.-F. Wu, C.-T. Huang, and C.-W. Wu, “RAMSES: a fast memory fault simulator,” in Proc. IEEE Int’l Symp. on Defect and Fault Tolerance in VLSI Systems (DFT), Nov. 1999, pp. 165–173. [96] H.-C. Lu and J.-F. Li, “A programmable online/off-line built-in self-test scheme for RAMs with ECC,” in Proc. IEEE Int’l Symp. on Circuits and Systems (ISCAS), May 2009, pp. 1997–2000. [97] L.-M. Denq, T.-C. Wang, and C.-W. Wu, “An enhanced SRAM BISR design with reduced timing penalty,” in Proc. IEEE Asian Test Symp. (ATS), Nov. 2006, pp. 25–30. [98] IEEE, “IEEE 1500 standard for embedded core test (SECT),” http://grouper.ieee.org/groups/1500/, 2005. [99] ——, IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture. Piscataway: IEEE Standards Department, May 1990. [100] J.-F. Li, H.-J. Huang, J.-B. Chen, C.-P. Su, C.-W. Wu, C. Cheng, S.-I. Chen, C.-Y. Hwang, and H.-P. Lin, “A hierarchical test scheme for system-on-chip designs,” in Proc. IEEE/ACM Design, Automation, and Test in Europe (DATE), Mar. 2002, pp. 486–490. [101] IEEE, IEEE Standard Testability Method for embedded core-based integrated circuits. Piscataway: IEEE Standards Department, Aug. 2005. [102] M. R. Ouellette, D. L. Anand, and P. Jakobsen, “Shared fuse macro for multiple embedded memory device with redundancies,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), May 2001, pp. 191–194. [103] B. Cowan, O. Fransworth, P. Jkobsen, S. Oakland, M. R. Ouellette, and D. L. Wheater, “On-chip repair and an ATE independent fusing methodology,” in Proc. IEEE Int’l Test Conf. (ITC), Oct. 2002, pp. 178–186. [104] D. Anand, B. Cowan, O. Fransworth, P. Jakobsen, S. Oakland, M. R. Ouellette, and D. L. Wheater, “An on-chip self-repair calculation and fusing methodology,” IEEE Design & Test of Computers, vol. 20, no. 5, pp. 67–75, Sept.-Oct. 2003. [105] L.-T. Wang, C.-W. Wu, and X. Wen, Design for Testability: VLSI Test Principles and Architectures. Elsevier (Morgan Kaufmann), 2006.
指導教授	李進福(Jin-Fu Li)	審核日期	2010-11-17
推文	facebook   plurk   twitter   funp   google   live   udn   HD   myshare   reddit   netvibes   friend   youpush   delicious   baidu
網路書籤	Google bookmarks   del.icio.us   hemidemi   myshare