不同佈局薄膜電容分析與玻璃基板覆晶之功率放大器設計

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姓名

周福興(Fu-Hsing Chou) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

不同佈局薄膜電容分析與玻璃基板覆晶之功率放大器設計
(A Study of Thin-film Capacitor Layout and Power Amplifier Integrated with Passive Devices on Glass)

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摘要(中)

本論文第一個部分是分析探討在單石微波積體電路設計中所常用的薄膜電容在相同單位面積下改變佈局設計的高頻特性，以了解何種形式下的薄膜電容能夠達到最佳的共振頻率。論文中薄膜電容製作是利用半導體製程將其製作於砷化鎵基板上，並設計了十一種薄膜電容佈局形式且固定面積為100 × 100μm2。為了得到其精確的共振頻率及品質因素特性，在論文中介紹四種去嵌入法，藉由量測與模擬結果可知二階段開路/直通去嵌入法與探針墊/開路/直通去嵌入法較適用於薄膜電容。
而第二個部分則是探討藉由國家晶片中心(National Chip Implementation Center)所提供的玻璃基板整合式被動元件(Glasses Integrated Passive Device, GIPD)製程，透過覆晶封裝技術(Flip-Chip)將玻璃基板上的被動元件與台積電 0.18 μm CMOS製程所設計的驅動/功率級串疊式元件(Cascode MOSFET)晶片整合為一1.8 GHz差動Class-E 功率放大器。此電路架構的主要特色在於將被動元件製作在高絕緣度的玻璃基板上，藉此改善以往被動元件製作於矽基板上所造成的基板損失與以往打線(wire bonding)造成的寄生電感所產生的寄生效應，使得飽和功率(saturation power)與功率附加增益(power added efficiency)能有所提升。

摘要(英)

The first part of this thesis is to study the high frequency performance of thin-film capacitor in different geometry with the same layout area and to investigate which capacitor can achieve the best self-resonant frequency for the monolithic microwave integrated circuit (MMIC) circuit design. The thin-film capacitors were fabricated on GaAs substrate by using semiconductor process. There are different layout styles, 11 types in total, were designed into an unit area of 100 × 100μm2. In order to obtain the precisely characteristics of self-resonant frequency and quality factor, the thin-film capacitors including RF pads were extracted by using de-embedding method. Four de-embedding method are introduced in the thesis. Based on the results from measurement and simulation, the de-embedding methods, 2-step/open/thru and the pad/open/thru, are suitable for the thin-film capacitance extraction.
The second part presents a differential-type Class-E power amplifier for 1.8 GHz wireless application in which the amplifier was integrated by a chip having a driving and a power cascode MOSFETs designed by TSMC 0.18μm CMOS technology and the passive components based on Glasses Integrated Passive Device(GIPD) process. This circuit architecture not only avoids the parasitic inductors from bonding wire but also reduces the loss of the passive components on silicon substrate. Because of the improvement using GIPD technique, the saturation power and the power added efficiency therefore can be enhanced in power amplifier design.

關鍵字(中)

★ 薄膜電容
★ 去嵌入法
★ 功率放大器
★ 玻璃基板

關鍵字(英)

★ power amplifier
★ de-embedding
★ MIM capacitor
★ glass substrate

論文目次

摘要..... IV
Abstract. V
致謝..... VI
圖目錄... IX
表目錄... XIV
第一章導論..... 1
1.1研究動機與目的. 1
1.2被動元件發展現況........ 4
1.3 Class-E 功率放大器研究發展現況.. 5
1.4論文架構....... 8
第二章不同佈局形式之薄膜電容特性. 9
2.1簡介.. 9
2.2去嵌入式方法(de-embedding method) 9
2.2.1 二階段開路/短路去嵌入法(2 step Open/short de-embedding method). 10
2.2.2 探針墊/開路/短路去嵌入法(Pad/Open/Short de-embedding method).. 13
2.2.3 二階段開路/直通去嵌入法(2 step Open/Thru de-embedding method). 18
2.2.4 探針墊/開路/直通去嵌入法(Pad/Open/Thru de-embedding method).. 21
2.3不同佈局形式薄膜電容設計 27
2.3.1 薄膜電容基本介紹..... 27
2.3.2 薄膜電容佈局設計..... 29
2.3.3 薄膜電容製作流程..... 34
2.4不同佈局形式薄膜電容特性分析..... 38
2.4.1 不同佈局形式薄膜電容值萃取流程 38
2.4.2 不同佈局形式薄膜電容模擬與量測結果..... 40
2.5並聯型式薄膜電容特性分析 .47
2.6結論.. 50
第三章與玻璃基板覆晶之差動串疊式Class-E功率放大器.. 51
3.1簡介.. 51
3.2 Class-E功率放大器操作原理....... 52
3.3玻璃基板整合式被動元件(Glasses Integrated Passive Device)製程簡介... 54
3.4電路設計....... 56
3.4.1差動串疊式Class-E放大器電路架構 56
3.4.2被動元件佈局考量...... 62
3.4.3電路模擬與量測........ 63
3.5結論.. 81
第四章結論..... 82
參考文獻. 83
附錄A 口試問題回答 86

參考文獻

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指導教授

辛裕明(Yue-Ming Hsin)

審核日期

2011-8-11

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