用於三維積體電路之溫度導向平面規劃的散熱型矽晶穿孔面積融合方法

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：28

、訪客IP：3.12.152.196

姓名

吳學謀(Hsueh-mou Wu) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

用於三維積體電路之溫度導向平面規劃的散熱型矽晶穿孔面積融合方法
(Thermal-Driven Floorplanning for 3D ICs Using Fusion of Thermal-TSV Area)

相關論文

★ 運算放大器之自動化設計流程及行為模型研究	★ 高速序列傳輸之量測技術
★ 使用低增益寬頻率調整範圍壓控震盪器之1.25-GHz八相位鎖相迴路	★ 類神經網路應用於高階功率模型之研究
★ 使用SystemC語言建立IEEE 802.3 MAC 行為模組之研究	★ 以回填法建立鎖相迴路之行為模型的研究
★ 高速傳輸連結網路的分析和模擬	★ 一個以取樣方式提供可程式化邏輯陣列功能除錯所需之完全觀察度的方法
★ 抑制同步切換雜訊之高速傳輸器	★ 以行為模型建立鎖相迴路之非理想現象的研究
★ 遞迴式類神經網路應用於序向電路之高階功率模型的研究	★ 用於命題驗証方式的除錯協助技術之研究
★ Verilog-A語言的涵蓋率量測之研究	★ 利用類神經模型來估計電源線的電流波形之研究
★ 5.2GHz CMOS射頻接收器前端電路設計	★ 適用於OC-192收發機之頻率合成器和時脈與資料回復電路

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

隨著科技日新月異，製程的進步使得元件尺寸逐漸縮小，積體電路（integrated circuit）來到了奈米（nanometer）製程技術的時代，惟元件尺寸的精進已接近其物理極限。除此之外，晶片內部連線所造成的延遲也日益嚴重，使得整個晶片的效能也出現了瓶頸。因此，現今的晶片設計上，設計者正朝著另一角度的思維開發新一代的設計技術。三維積體電路（three dimensional integrated circuit）被視為能有效地改善上述問題的一項技術。然而，晶片從二維架構轉變為三維架構，雖然能有較好的面積、效能和功率消耗，但也引發出許多問題，溫度就是其中一項重要且不可忽略的議題。溫度議題的起因主要來自於堆疊技術易造成晶片中某些位置不易散熱，而晶片內部嚴重過熱將導致晶片毀損。插入散熱型矽晶穿孔（thermal through-silicon-via）於三維積體電路內部是一項可以有效解決三維積體電路內部散熱問題的技術。由於散熱型矽晶穿孔的尺寸遠大於標準元件的尺寸，所以如果在實體設計初期即適當地規劃散熱型矽晶穿孔的位置，便可以提早避免因擺置散熱型矽晶穿孔空間不足而造成設計佈局需要大幅變動，因此有許多研究提出在平面規劃（floorplanning）階段以推開電路區塊（block）並插入散熱型矽晶穿孔方式解決散熱的問題。
本論文中，提供一個不同於以往的設計思維。在平面擺置之前即估計需要插入的散熱型矽晶穿孔數量，並根據這些數量擴大電路區塊後再進行平面規劃。平面規劃過程中除了須考量傳統面積及線長的最佳化外，還須同時考量電路區塊擴大區域的融合（fusion）程度，以期使用最少的散熱型矽晶穿孔數量達到要求的晶片內部目標溫度。

摘要(英)

As the process technology advances, the device size of integrated circuits continues to shrink into the nanometer scale. However, the device size is nearing its physical limits. Besides, interconnect delays are also growing, incurring the bottleneck of chip performance. Therefore, designers are thinking of moving to another point to develop a new generation of design technologies. Three dimensional integrated circuits (3D IC) are proposed as one technology to solve these problems. However, although 3D IC designs have better chip size, performance, and power consumption than 2D IC designs have, many emergent issues are occurred. Temperature is one of important issues and cannot be ignored. The temperature issue is mainly from the stacking technology which makes the thermal inside a chip cannot be dissipated easily. Thus, an overheating chip will incur the chip failed. Thermal through-silicon-via (TTSV) insertion technology is an effective method to dissipate the thermal in 3D IC. Since the size of a TTSV is much larger than that of a standard cell, space shortage and layout modification can be avoided if the TTSV location are planned in an early physical design stage. Thus, many researches proposed TTSV insertion by a push-block method to solve this issue during floorplanning.
In this thesis, we propose a new viewpoint for TTSV insertion. The required number of TTSVs for each block is estimated and is used to enlarge the block before floorplanning. During floorplanning, we not only minimize area and wirelength, but also maximize the effect of fusion of TTSV area. Our objective is to satisfy the target temperature inside a chip with minimum number of TTSVs.

關鍵字(中)

★ 溫度
★ 三維積體電路
★ 平面規劃

關鍵字(英)

★ floorplan
★ thermal
★ 3DIC

論文目次

第一章、緒論 1
1-1 3D IC 介紹 1
1-2 矽晶穿孔技術 3
1-3 堆疊技術 5
1-4 三維積體電路的挑戰7
1-5 論文結構 10
第二章、背景 11
2-1 降溫方法 11
2-2 熱分析模型14
2-2-1 等效電阻熱分析模型14
2-2-2 熱點分析模型 16
2-3 溫度效應的考慮時機 19
2-3-1 在平面規劃時考量熱效應19
2-3-2 在擺置時考量熱效應24
2-3-3 繞線時考慮熱效應 26
2-4 比較 28
2-5 散熱型矽晶穿孔的空間規劃30
第三章、融合平面規劃法 35
3-1 動機 35
3-2 問題定義 37
3-3 流程 38
3-4 溫度計算 39
3-5 區塊擴大 41
3-6 模擬退火演算法（Simulated Annealing）43
3-7 B*-tree 可融合平面規劃46
3-9 計算散熱型矽晶穿孔數50
第四章、實驗結果與分析 51
4-1 實驗環境與設定 51
4-2 實驗結果 52
第五章、結論與未來展望 56
第六章、參考文獻57

參考文獻

[1] Jian-Qiang Lu, “3-D Hyperintegration and Packing Technologies for Micro-Nano Systems,” Proc. IEEE, January, 2009, pp. 18 – 30.
[2] THE INTERNATIONAL TECHNOLOGY ROADMAP FOR SEMICONDUCTORS: 2009.
[3] Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee, Sung Kyu Lim, David Z. Pan, “TSV Stress Aware Timing Analysis with Applications to 3D-IC Layout Optimization,” in Proc. Design Automation Conf., 2010, pp. 803 – 807.
[4] Cheng-Chi Chan, Yen-Ting Yu, Iris Hui-Ru Jiang, “3DICE: 3D IC Cost Evaluation Based on Fast Tier Number Estimation,” in Pro. International Symposium on Quality Electronic Design, 2011, pp. 1 – 6.
[5] Chia-Jen Chang, Pao-Jen Huang, Tai-Chen Chen, Chien-Nan Jimmy Liu, “ILP-based inter-die routing for 3D ICs,” in Proc. Asia South Pacific Des. Auto. Conf., 2011, pp.330 – 335.
[6] Van der Plas Geert, Limaye Paresh, Loi Igor, Mercha Abdelkarim, Oprins Herman, Torregiani Cristina, Thijs Steven, Linten Dimitri, Stucchi Michele, Katti Guruprasad, Velenis Dimitrios, Cherman Vladimir, Vandevelde Bart, Simons Veerle, De Wolf Ingrid, Labie Riet, Perry Dan, Bronckers Stephane, Minas Nikolaos, Cupac Miro, RuythoorenWouter, Van Olmen Jan, PhommahaxayAlain, de ten Broeck Muriel de Potter, Opdebeeck Ann, Rakowski Michal, De Wachter Bart, Dehan Morin, Nelis Marc, Agarwal Rahul, Pullini Antonio, Angiolini Federico, Benini Luca, Dehaene Wim, Travaly Youssef, Beyne Eric, Marchal Paul, “Design Issues and Considerations for Low-Cost 3-D TSV IC Technology,” IEEE Journal of Solid-State Circuits, 2010, pp 293 – 307
[7] Sung Kyu Lim, “TSV-Aware 3D Physical Design Tool Needs for Faster Mainstream Acceptance of 3D ICs,” ACM DAC Knowledge Center （dac.com）, 2010.
[8] Vyshnavi Suntharalingam, Robert Berger, James A. Burns, Chenson K. Chen, Craig L. Keast, Jeffrey M. Knecht, Renee D. Lambert, Kevin L. Newcomb, Daniel M. O’Mara, Dennis D. Rathman, David C. Shaver, Antonio M. Soares, Charles N. Stevenson, Brian M. Tyrrell, Keith Warner, Bruce D. Wheeler, Donna-Ruth W. Yost, Douglas J. Young, “Megapixel cmos image sensor fabricated in three-dimensional integrated circuit technology,” IEEE International Solid-State Circuits Conference, 2005. pp 356 – 357.
[9] Zhang Xu and Jiang Xiaohong, “Redundant Vias Insertion for Performance Enhancement in 3D ICs,” IEICE Trans. on electronic, 2008, pp. 509 – 519.
[10] George Karypis and Vipin Kumar, “Multilevel k-way Hypergraph Partitioning,” in Proc. Design Automation Conf., 1999, pp. 343 – 348.
[11] Mohit Pathak, Young-Joon Lee, Thomas Moon, Sung Kyu Lim, “Through-silicon-via management during 3d physical design: When to add and how many?” in Proc. Int. Conf. Computer-Aided Des., 2010, pp. 387 – 394.
[12] Patrick Wilkerson, Michal Furmanczyk, Marek Turowski, “Compact thermal modeling analysis for 3D integration circuits,” in Proc. Int. Conf. Mixed Des. Integer. Circuits and Syst., 2004, pp. 24 – 26.
[13] Patrick Wilkerson, Ashok Raman, Marek Turowski, “Fast, Automated Thermal Simulation of Three-Dimensional Integrated Circuits,” in Proc. Int’l Conf. on Thermal and Thermomechanical Phenomena in Electronic Systems, 2004, pp. 706 – 713.
[14] Wei Huang, Mircea R. Stan, Kevin Skadron, Karthik Sankaranarayanan, Shougata Ghosh, Sivakumar Velusamy, “Compact Thermal Modeling for Temperature Aware Design,” in Proc. Design Automation Conf., 2004, pp 878 – 883.
[15] Oprins Herman, Cherman Vladimir, Stucchi Michele, Vandevelde Bart, G Van der Plas, Marchal Paul, Beyne Eric, “Steady State and Transient Thermal Analysis of Hot Spots in 3D Stacked ICs using Dedicated Test Chips,” Semiconductor Thermal Measurement and Management Symposium, Conf., 2011, pp. 131 – 137.
[16] Torregiani Cristina, Oprins Herman, Vandevelde Bart, Beyne Eric, Wolf. I. De, “Compact Thermal Modeling of Hot Spots in Advanced 3D-Stacked ICs,” in Proc. Electronics Packaging Technology Conference, 2009, pp. 131 – 136.
[17] Young- Joon Lee, Rohan Goel, Sung Kyu Lim, ”Multi-functional Interconnect Co-optimization for Fast and Reliable 3D Stacked ICs”, in Proc. Int. Conf. Computer-Aided Des., 2009, pp. 645 – 651.
[18] Michal Furmanczyk, Patrick Wilkerson, Andrzej Przekwas, ” Multiphysics modeling of integrated microfluidic-thermoelectric cooling for stacked 3D ICs”, Semiconductor Thermal Measurement and Management Symposium, 2003, pp. 35 – 41.
[19] Oprins Herman, Cherman Vladimir, Torregiani Cristina, Stucchi Michele, Vandevelde Bart, Beyne Eric, ” Thermal test vehicle for the validation of thermal modelling of hot spot dissipation in 3D stacked ICs”, Electronic System-Integration Technology Conference （ESTC）, 2010, pp. 1 – 6.
[20] CFD-ACE+ Module Manual, Vol. I, Version 2002.
[21] Jason Cong, Jie Wei, Yan Zhang, "A Thermal-Driven Floorplanning Algorithm for 3D ICs," in Proc. Int’l Conf. on Computer-Aided Design, November, 2004, pp. 306 – 313.
[22] Jason Cong, Ashok Jagannathan, Yuchun Ma, Gleen Reinman, Jie Wei, Yan Zhang, “An Automated Design Flow for 3D Microarchitecture Evaluation,” in Proc. Asia South Pacific Des. Auto. Conf., 2006.
[23] Pingqiang Zhou, Yuchun Ma, Zhouyuan Li, Robert P. Dick, Li Shang, Hai Zhou, Xianlong Hong, Qiang Zhou, “3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits,” in Proc. Int. Conf. Computer-Aided Des., 2007, pp.590 – 597.
[24] Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Wenjian Yu, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng, “Efficient thermal via planning approach and its application in 3-D floorplanning,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006, pp. 645 – 658.
[25] Shun-Hua Lin, Jin-Tai Yan, Herming Chiueh, “Block-Level Thermal Model for Floorplan Stage in VLSI Design Flow,” in Proc. Thermal Inveatigation of ICs and Systems, Conf., 2008, pp 58 – 64.
[26] Brent Goplen and Sachin Sapatnekar, “Thermal via Placement in 3D ICs,” in Proc. Int. Symp. Phys. Des., April 2005, pp. 167 – 174.
[27] Jason Cong and Yan Zhang, " Thermal via planning for 3-D ICs," in Proc. Int’l Conf. on Computer-Aided Design, 2005, pp. 745 – 752.
[28] Jason Cong and Yan Zhang, “Thermal-driven multilevel routing for 3-D ICs,” in Proc. Asia South Pacific Des. Auto. Conf., January 2005, pp. 121–126.
[29] Tianpei Zhang, Yong Zhan, and Sachin S. Sapatnekar, “Temperature-aware routing in 3D ICs,” in Proc. Asia South Pacific Des. Auto. Conf., January 2006, pp. 309–314.
60
[30] Wei-lun Hung, Greg M. Link, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin, “Interconnect and Thermal-aware Floorplanning for 3D Microprocessors,” in Proc. Int’l Symp. on Quality Electronic Design, 2006, pp. 98 – 104.
[31] Ting-Yen Chiang, Kaustav Banerjee, Krishna C. Saraswat, “Effect of Via Separation and Low-k Dielectric Materials on the Thermal Characteristics of Cu Interconnects,” IEEE International Electron Devices Meeting, IEDM Technical Digest, IEEE Press, 2000, pp.681–684.
[32] Jing Li, Hiroshi Miyashita, “Efficient Thermal Via Planning for Placement of 3D Integrated Circuits,” ISCAS, 2007, pp. 145 – 148.
[33] Kan Wang,Yuchun Ma, Sheqin Dong, Yu Wang, Xianlong Hong, Jason Cong, “Rethinking Thermal Via Planning with Timing–Power -Temperature Dependence for 3D ICs” in Proc. Asia South Pacific Des. Auto. Conf., 2011, pp 261 – 266.
[34] Xin Li, Yuchun Ma, Xianlong Hong, Sheqin Dong, J. Cong, “LP Based White Space Redistribution for Thermal Via Planning and Performance Optimization in 3D ICs,” in Proc. Asia South Pacific Des. Auto. Conf., 2008, pp 209 – 212.
[35] Yun-Chih Chang, Yao-Wen Chang, Guang-Ming Wu, Shu-Wei Wu, “B*-tree: A new representation for non-slicing floorplans,” in Proc. Design Automation Conf., 2000, pp. 458 – 463.
[36] Scott Kirkpatrick, C. Daniel Gelatt, Mario P. Vecchi, “Optimization by Simulated Annealing,” Science, vol. 220, 1983, pp. 671 – 680.
[37] Lei Cheng, Liang Deng, Martin D. F.Wong, “Floorplanning for 3-D VLSI design,” in Proc. Asia South Pacific Des. Auto. Conf., January. 2005, pp. 405 – 411.

指導教授

陳泰蓁、劉建男
(Tai-Chen Chen、Chien-Nan Jimmy Liu)

審核日期

2011-8-15

推文