垂直十字鏈基板結構應用於矽穿孔雜訊評估

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姓名

李孟穎(Meng-Ying Lee) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

垂直十字鏈基板結構應用於矽穿孔雜訊評估
(TSV Noise Evaluation by Using the Vertical-Cross-Chain Substrate Structure)

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至系統瀏覽論文 ( 永不開放)

摘要(中)

隨著三維晶片(3D IC)裡的矽穿孔(TSV)密度增加，兩訊號間互相干擾將會造成訊號傳輸品質發生問題。矽穿孔(TSV)串音干擾主要的因素取決於矽穿孔(TSV)的尺寸及矽穿孔(TSV)之間的間距(Spacing)。此外，矽基板(Slicon Substrate)的厚度及參雜濃度也發揮了重要的作用，它們影響基板接地的有效性。
本論文主要提出等效垂直十字鏈基板結構(Vertical-Cross-Chain Substrate Structure ; VCCSS)分析平台，針對矽穿孔(TSV)之間的耦合效應及使用屏蔽技巧(Shielding Technique)來加強模擬，並且在不同條件下做分析其包括矽基板浮接(Substrate Floating)、矽基板接地(Substrate Grounding)、保護環(Guard Ring)及接地矽穿孔(TSV Ground)。展現出從矽穿孔(TSV)底部到頂部基板接地會有一收集發散電流的深度效應。從串音干擾預防的觀點來看，無論是矽基板接地(Substrate Grounding)或是接地矽穿孔(Ground TSV)的方式皆比使用間距(Spacing)來的有效。

摘要(英)

As for the Through-Silicon-Via (TSV) density increasing in the three-dimensional chip integration, the quality of signal transmission may be a problem on the signal interfering. The major factors of TSV crosstalk are determined by the size of TSVs and their spacing between two TSVs. In addition, the thickness of silicon dioxide and the doping concentration of the silicon substrate also play a key role, where they determine the total energy injecting into the substrate and the effectiveness of substrate grounding, respectively.
In this thesis, a noise analysis platform for an advanced TSV model, called Vertical-Cross-Chain Substrate Structure (VCCSS), is proposed to discuss with the coupling and guarding effects including substrate floating, substrate grounding, p+ guard-ring and TSV ground on the TSV coupling. Besides of the effects for each situation, especially for substrate vertical effect, it is also shown the quantitative measure and better ways to prevent the interaction between signals.

關鍵字(中)

★ 耦合雜訊
★ 參雜濃度
★ 矽基板
★ 矽穿孔
★ 三維晶片

關鍵字(英)

★ 3D IC
★ Coupling Noise
★ Doping Concentration
★ Silicon Substrate
★ TSV

論文目次

摘要 I
Abstract II
目錄 III
圖目錄 V
表目錄 VII
第一章緒論 1
1.1 研究背景簡介 1
1.2 研究動機 3
1.3 論文架構 4
第二章信號完整性概論 5
2.1 串音現象基本簡介 5
2.2 串音現象之雜訊來源 6
2.3 串音現象之效應 11
2.3.1 脈衝干擾電壓 11
2.3.2 延遲時間 12
2.3.3阻尼震盪 14
2.3.4抖動 14
第三章矽穿孔模型(TSV Model) 16
3.1 矽穿孔(TSV)介紹 16
3.1.1 三維晶片(3D IC)說明 16
3.1.2 矽穿孔(TSV)不同的名詞 17
3.2 矽穿孔(TSV)製成 18
3.2.1先鑽孔(Via First) 18
3.2.2後鑽孔(Via Last) 20
3.3 矽穿孔(TSV)本質結構與等效模型 21
3.3.1矽穿孔(TSV)本質結構 21
3.3.2矽穿孔(TSV)等效模型 23
3.3.3 VCCSS等效模型 29
第四章矽穿孔(TSV)耦合雜訊分析 32
4.1 矽基板(Silicon Substrate)之參雜濃度 32
4.2 Aggressor-Victim Pair 34
4.2.1 Aggressor-Victim Pair的架構 34
4.2.2 不同環境下的Aggressor-Victim Pair耦合雜訊 35
4.3 抑制矽穿孔(TSV)耦合雜訊 38
第五章矽穿孔(TSV)耦合雜訊實驗結果 39
5.1 解析平台的建立 39
5.2 Aggressor-Victim Pair模擬結果 42
5.3 Signal Bus 49
5.3.1 Multiple Victims 51
5.3.2 Multiple Aggressors 53
第六章結論 57
參考文獻 58

參考文獻

[1] 唐經洲, “為何不用SoC？,” CTimes,零組件雜誌,四月號2009.
[2] 唐經洲, “3D IC有其他好處嗎？,” CTimes,零組件雜誌, 五月號, 2009.
[3] 張嘉華, 唐經洲, “3D IC應用市場核心技術TSV的概況與未來,” CTimes, 零組件雜誌, 九月號2009.
[4] 鈴木茂夫著, 白中和譯, “容易瞭解的高頻技術入門,” 建興文化事業有限公司 2007.
[5] 陳耿男, “匯流排上的時間延遲及交談失真的偵錯設計技巧,” 國立中央大學電機工程學系碩士論文 2006.
[6] “Market trends for 3D stacking,” Yole, Tech. Rep., 2008, http://www.emc3d.org/documents/library/marketAnalysis_3D/YOLE3D%20IC.pdf.
[7] J. Cho, J. Shim, E. Song, J.S. Pak, J. Lee, H. Lee, K. Park and J. Kim, “Active Circuit to Through Silicon Via (TSV) Noise Coupling,” IEEE Conference on Electrical Performance of Electronic Packaging and Systems 2009, pp. 97-100, Oct. 2009.
[8] G. Katti, M. Stucchi, K. De Meyer, and W. Dehaene, “Electrical Modeling and Characterization of Through-Silicon Vias (TSVs) for 3-D Integrated Circuits,” IEEE Transactions on Electron Devices, pp. 256-262, Jan. 2010.
[9] R. Gharpurey, and R. G. Meyer, “Modeling and Analysis of Substrate Coupling in Integrated Circuits,” IEEE Journal of Solid-State Circuits, pp. 344-353, Mar. 1996.
[10] 游祥凱, “使用於矽穿孔耦合分析之垂直十字鏈基板結構,” 國立中央大學電機工程學系碩士論文 2010.
[11] R. Weerasekera, M. Grange, D. Pamunuwa, H. Tenhunen, and L.R. Zheng, “Compact Modelling of Through-Silicon Vias (TSVs) in Three-Dimensional (3-D) Integrated Circuits,” IEEE International Conference on 3D System Integration 2009, pp. 1-8, Sep. 2009.
[12] N.H. Khan, S.M. Alam, and S. Hassoun, “Through-Silicon Via (TSV)-induced noise characterization and noise mitigation using coaxial TSVs,” IEEE International Conference on 3D System Integration 2009, pp. 1-7, Sep. 2009.
[13] From:J. Cho; J. Kim; T. Song; J. S. Pak; J. Kim; H. Lee; J. Lee; K. Park, “Through silicon via (TSV) shielding structures Through,” IEEE Conference on Electrical Performance of Electronic Packaging and Systems 2010, pp. 269 - 272 , Oct. 2010
[14] L. Hui Chen and M. Marek-Sadowska, “Aggressor Alignment for Worst-Case Crosstalk Noise,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 612–621, May 2001.
[15] J. Pak, C. Ryu, and J. Kim, “Electrical Characterization of Through Silicon Via (TSV) depending on Structural and Material Parameters based on 3D Full Wave Simulation,” International Conference on Electronic Materials and Packaging 2007, pp. 351-354, May 2008.
[16] S.W. Tu, Y.W. Chang, and J.Y. Jou, “RLC Coupling-Aware Simulation and On-Chip BUS Encoding for Delay Reduction,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 2258-2264, Oct. 2006.
[17] C. Ryu, J. Lee, H. Lee, K. Lee, T. Oh, and J. Kim, “High Frequency Electrical Model of Through Wafer Via for 3-D Stacked Chip Packaging,” Electronics System integration Technology Conference, pp.215-220, Sep. 2006.
[18] E. Salman, and E. G. Friedman, “Methodology for placing localized guard rings to reduce substrate noise in mixed-signal circuits,” Research in Microelectronics and Electronics 2008, pp. 85-88, Apr. 2008.
[19] J. S. Yang, and A.R. Neureuther, “Crosstalk Noise Variation Assessment and Analysis for the Worst Process Corner,” International Symposium on Quality Electronic Design 2008, pp. 352-356, Mar.2008.
[20] J. Kim, E. Song, J. Cho, J.S. Pak, J. Lee, H. Lee, K. Park, and J. Kim, “Through silicon via (TSV) equalizer,” IEEE Conference on Electrical Performance of Electronic Packaging and Systems 2009, pp. 13-16, Oct. 2009.
[21] T. Bandyopadhyay, R. Chatterjee, C. Daehyun, M. Swaminathan, and R. Tummala, “Electrical modeling of Through Silicon and Package Vias,” IEEE International Conference on 3D System Integration 2009, pp. 1-8, Sep. 2009.
[22] P. Y. Wu, S.Y.S. Tsui, and P.K.T. Mok, “Area- and power-efficient monolithic buck converters with pseudo-type III compensation, ’’ IEEE J. Solid-State Circuits, vol.45, no.8, pp.1446-1455, Aug. 2010.
[23] [20] K. J. Chang, N. H. Chang, S. Y. Oh, and K. Lee, “Parameterized SPICE Subcircuits for Multilevel Interconnect Modeling and Simulation,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, pp. 779–789, Nov. 1992.

指導教授

陳竹一(Jwu-E Chen)

審核日期

2011-11-4

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