摘要(英) |
In portable and implementable biomedical systems, there are two more important design issues in the biomedical chip than other applications, which are very low power consumption and low power supply voltage. Besides, the low power design has to effectively shrink down the chip area and battery volume to satisfy portable and long battery lifetime requirements of biomedical instruments.
The high resolution and low power analog-to-digital converter (ADC) is a key component in biomedical systems. By taking the advantage of oversampling technique, the sigma-delta (SD) modulation can relax the design complexity of the analog front end anti-aliasing filter. However, the SD ADC needs the digital decimation filter at the SD modulator output to remove the high frequency noise and down-sampling data.
This study proposes a low power and minimized circuit area digital decimation filter design in the SD ADC. Poly-phase decomposition, canonical signed digit (CSD) and common sub-expression sharing (CSE) approaches are applied in the design to achieve low power target. Furthermore, the “search method to minimize filter area” is also proposed to find out the filter coefficients with minimized circuit area and suitable performance. The proposed design is first realized on Altera FPGA emulation board. The performance can achieve 73dB signal-to-noise and distortion ratio (SNDR) and 12bits resolution. Our design is also accomplished in TSMC 0.13um CMOS process with 305uW power consumption and 0.40mm2 chip area to demonstrate the proposed digital decimation filter design in the SD ADC.
|
參考文獻 |
[1] 戴邦傑,“Sigma-Delta Modulator for Biomedical Signal Processing”,國立中央大學,電機工程系碩士論文,民國九十九年
[2] S. R. Norsworthy, R. Schreier and G.C. Temes, Delta-Sigma Data Converters, IEEE Press, 1997.
[3] D. A. Johns and K. Martin, Analog Integrated Circuit Design: John Wiley and Sons, 1997.
[4] H. Abraham, Probabilistic System and Random Signals: Prentice Hall, 2006.
[5] R. Carley and J. Kenny, “A 16-bit 4’th order noise-shaping D/A converter,” Proceedings of the 1988 IEEE Custom Integrated Circuits Conference, pp.21.7/1-21.7/4, Rochester, NY, May 1988.
[6] E. B. Hogenauer, “An Economical Class of Digital Filters for Decimation and Interpolation,” IEEE Trans. Acoustics, Speech and Signal Processing, vol.29, pp.156-162, April 1981.
[7] Altera “Understanding CIC Compensation Filters,” Altera Application Note 455, April 2007.
[8] A. Gerosa and A. Neviani, “A low-power decimation filter for A sigma-delta convertor based on a power-optimized Sinc filter,” Circuits and Systems, 2004, ISCAS ‘04, vol.2, pp. II-245-8, May 2004.
[9] P. P. Vaidyanathan, “Multirate digital filters, filter banks, polyphase networks, and applications: a tutorial,” Proc. of the IEEE, vol. 78, No.1, pp. 56-93, Jan. 1990.
[10] R. I. Hartley, ”Subexpression sharing in filters using canonic signed digit multipliers,” IEEE Trans. Circuits Syst. II, vol. 43, pp. 677-688, Oct 1996.
[11] H. Aboushady, Y. Dumonteix, M. -M. Louerat and H. Mehrez, ”Efficient polyphase
|