使用可調式負載及面積縮放技巧提升功率放大器之效率

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姓名

王珮暻(Pei-ching Wang) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

使用可調式負載及面積縮放技巧提升功率放大器之效率
(Power Amplifier Efficiency Enhancement Using Tunable Load and Area Resizing Techniques)

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摘要(中)

功率放大器是射頻前端功率消耗最多的單一電路元件，因此提升其將直流功率轉換為射頻功率的效率對系統整體功耗的降低有長足影響。本論文將討論可調式負載及面積縮放這兩個效率改善技巧，並將之用於CMOS功率放大器設計實際驗證之。
我們設計了兩個操作於2.535 GHz使用可調式負載及面積縮收技巧的功率放大器，皆使用TSMC 0.18-μm CMOS製程實現。第一個放大器具有兩路面積切換及兩種負載阻抗切換；在3.3 V供應電壓下，此功率放大器之P1dB為23.1 dBm，相對應之PAE為31.2%。使用面積縮放及負載切換，在大於3-dB功率回退的情況下，直流功耗可降低40%以上。第二個放大器具有八路面積切換及兩種負載阻抗切換，並包含一適用於多路面積切換的旁路電容共用設計；在3.3 V供應電壓下，模擬之P1dB為21.2 dBm，相對應之PAE為30.6%；在3-dB功率回退的情況下，可使直流功耗降低40%。
我們成功地驗證結合面積縮放及可調式負載技巧可有效降低功率放大器於低功率區的直流功率消耗，並大幅提升其效率。

摘要(英)

A power amplifier (PA) is the most power-hungry circuit block in a RF frontend. Increasing its efficiency of transferring the DC power to RF power is therefore eminent when it comes to reducing the DC power consumption of RF systems. This thesis discusses two efficiency-enhancing techniques, namely, tunable load and area resizing. The techniques are applied to and verified by two CMOS PA designs.
Based on tunable-load and area-resizing techniques, two switchable PAs operating at 2.535 GHz are designed and implemented in TSMC 0.18-μm CMOS technology. The first PA can be switched between two states; each state has a different transistor size and corresponds to a different load impedance. At 3.3-V supply voltage, the P1dB and the corresponding PAE are 23.1 dBm and 31.2%, respectively. By resizing the area and switching the load impedance, the DC power consumption of the PA can be reduced by more than 40% as the power is backed off by 3 dB or more. The second PA has 8 area-resizing states and its load impedance can be switched between two different values. In addition, it contains a bypass-capacitor-sharing design that suits area-resizing with multiple controls. Simulation results show, at 3.3-V supply, the P1dB and the corresponding PAE are 21.2 dBm and 30.6%, respectively. The DC power consumption is reduced by 40% at 3-dB power back-off.
It is successfully demonstrated that, combining area resizing and tunable load techniques, the DC power consumption of PAs at low-power region can be effectively reduced and the power efficiency can be significantly enhanced.

關鍵字(中)

★ 功率放大器
★ 可調式負載

關鍵字(英)

★ Power Amplifier
★ Tunable Load

論文目次

目錄
摘要 I
Abstract II
第一章緒論 1
1–1研究動機 1
1–2文獻回顧 3
1–2–1 可調式匹配網路 5
1–2–2 面積縮放 6
1–3章節介紹 7
第二章使用可切換式匹配及面積縮放技巧以提升效率之功率放大器 8
2–1簡介 8
2–2可切換式功率放大器設計 10
2–2–1 面積縮放技巧 12
2–2–2 可切換式匹配網路 14
2–2–3 可切換式電容 19
2–2–4 可切換式功率放大器 22
2–3電路模擬與量測結果 26
2–3–1 S參數量測結果與偵錯 26
2–3–2 FIB後S參數與大訊號模擬量測之結果 32
2–3–3 量測與偵錯結果比較 38
2–4 結果與討論 44
第三章具多路面積切換功能之可切換式功率放大器 47
3–1簡介 47
3–2可切換式功率放大器 48
3–2–1面積縮放技巧 49
3–2–2可切換式匹配網路 53
3–2–3可切換式功率放大器 55
3–3模擬結果 60
3–4量測結果 67
3–4–1 佈局圖偵錯 67
3–4–2 FIB後S參數與大訊號模擬量測之結果 69
3–5結果與討論 74
第四章結論 75
4–1結果與討論 75
4–2未來研究方向 76
參考文獻 77

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指導教授

傅家相(Jia-Shiang Fu)

審核日期

2012-7-23

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