全數位快速鎖定四相位同步複製延遲電路

以作者查詢圖書館館藏

、以作者查詢臺灣博碩士

、以作者查詢全國書目

、勘誤回報

、線上人數：46

、訪客IP：52.15.112.69

姓名

葉蔭平(Yin-ping Yeh) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

全數位快速鎖定四相位同步複製延遲電路
(An All Digital Fast Locked Four-Phase Synchronous Mirror Delay Circuit)

相關論文

★ 一種應用於觸控液晶顯示器的新型嵌入式開關	★ 多重相位之延遲鎖定迴路倍頻器設計與分析
★ 2.5Gbps串列收發器設計	★ 具低抖動與可適應式頻寬之自我偏壓鎖相迴路設計
★ 應用於串列傳輸之2.5GB/s CMOS 超取樣資料回復電路	★ 全數位任意責任週期之同步映射延遲電路
★ 全數位式互補金屬氧化半導自我取樣延遲線電路用於時脈抖動量測	★ 500MHz,30個相位輸出之鎖相迴路應用於三倍超取樣時脈回復系統
★ 設計於90奈米製程輸出頻率為100MHz-1GHz之具可適應性頻寬鎖相迴路	★ 高解析度可變動責任週期之同步複製延遲電路
★ 奈米CMOS晶片內序列傳輸之接收器	★ 奈米CMOS晶片內序列傳輸之送器
★ 基於鎖相迴路之多重相位脈波產生器	★ 低能量時脈儲存元件之分析、設計與量測
★ 具有預先增強器之Gbps串列連結傳送器及全數位超取樣資料回復器	★ 應用於10Gbps晶片系統傳輸鏈之低抖動自我校準鎖相迴路設計

檔案

[Endnote RIS 格式]

[Bibtex 格式]

[相關文章]

[文章引用]

[完整記錄]

[館藏目錄]

[檢視]

[下載]

本電子論文使用權限為同意立即開放。
已達開放權限電子全文僅授權使用者為學術研究之目的，進行個人非營利性質之檢索、閱讀、列印。
請遵守中華民國著作權法之相關規定，切勿任意重製、散佈、改作、轉貼、播送，以免觸法。

摘要(中)

在系統晶片中，隨著速度越來越快，頻率不斷的提升，訊號同步電路扮演著關鍵性的角色，鎖相迴路和延遲鎖定迴路被廣泛地使用在晶片設計裡，但是，此兩種電路在特性上具有幾個問題，第一，由於上述兩種電路屬於閉迴路系統，產生頻寬方面的問題，需要考慮電路穩定性的問題。第二，電路花費較長的時脈週期才能完成輸入訊號以及輸出訊號的相位鎖定，在鎖定過程中需要較大的功率消耗，於是，同步複製延遲電路被設計出來，藉此改善上述的問題。
傳統的同步複製延遲電路仍然有一些缺點，電路的相位誤差會受到輸出負載改變的影響而加大。另外，電路不具有多相位輸出，而且單位元件延遲時間太大導致電路的解析度不足。
本論文提出一個具有四相位快速鎖定之時脈同步複製延遲電路，不僅擁有同步複製延遲電路的優點：快速鎖定與好的穩定性，並且擁有四相位的輸出訊號以及較高的解析度。本電路是以TSMC 90 nm 1P9M CMOS製程實現晶片，供應電壓為1.2 V，本電路的操作在頻率是在690 MHz ~ 1.38 GHz。在頻率1.38 GHz時的功率消耗為30mW。整體晶片面積為542 × 583 um2，內部核心電路的面積為81 × 267 um2，輸出訊號之最大抖動量(peak-to-peak jitter)為5.65 ps。

摘要(英)

The development and main stream of system-on-chip (SoC) are highly integration and higher operation speed. Therefore, in order to suppress the clock skew, the clock synchronization circuit plays an important role in designing SoC system. Phase-Locked loop (PLL) and delay-locked loop (DLL) are often applied in many synchronization-dependent systems. However, these circuits have to consider some problems in using. First, the PLL and DLL have issues of loop bandwidth because they are both closed loop systems. For this reason, they need to consider the loop stability problem of circuits. Second, they need more time to synchronize the input and output clock signals. It consumes a lot of power in the process of locking. Consequently, the synchronous mirror delay (SMD) circuits were developed to solve above problem.
However, there are some drawbacks in conventional SMD. The phase error will increase because of the various output loading. Moreover, they cannot generate multi-phase out and the poor timing resolution due to the delay cell.
A four-phase high precision fast locking synchronization mirror delay circuit is proposed in the thesis. Which not only keeps the advantage of SMD, fast locking and stability issue, but also have four-phase and high resolution output. The chip is designed in a 90-nm CMOS process and the supply voltage is 1.2V. It operation frequency range is from 690 MHz to 1.38 GHz. The chip consumes 30mW power when the operating frequency is 1.38GHz. The chip area with I/O pads is 542 × 583 um2 . Internal active area without I/O pads is 81 × 267 um2. The maximum peak-to-peak jitter is 5.65 ps.

關鍵字(中)

★ 全數位
★ 四相位
★ 快速鎖定

關鍵字(英)

★ fast locked
★ all digital
★ four-phase

論文目次

摘要 ……………………………………………………………………………. I
Abstract ………………………………………………………………………….Ⅱ
目錄………………………………………………………………………………Ⅲ
圖目錄 …………………………………………………………………………...V
表目錄…………………………………………………………………………….VII
第1章緒論 1
1.1 研究動機 1
1.2 同步複製延遲電路的應用 2
1.3 論文架構 4
第2章相關電路的分析 5
2.1 相關電路之簡介 5
2.2 傳統式同步複製延遲電路 7
2.3 插入式同步複製延遲電路 9
2.4 省面積的插入式同步複製延遲電路 10
2.5 直接誤差偵測型同步複製延遲電路 11
2.6 數位類比混合式同步複製延遲電路 12
2.7 逐步近似式同步複製延遲電路 13
2.8 任意責任週期之同步複製延遲電路 14
2.9 電路特性之分類比較 15
第3章全數位快速鎖定四相位同步複製延遲電路 16
3.1 設計概念 16
3.2 諧波失真、阻塞鎖定之考量 17
3.3 電路架構及操作原理 20
3.4 粗調延遲電路 21
3.4.1 可調延遲電路 22
3.4.2 邊緣偵測器 25
3.4.3 量測延遲電路及複製控制電路 26
3.5 細調延遲電路 28
3.5.1 相位比較器 29
3.5.2 逐漸近似暫存器 31
3.5.3 解碼器 32
3.6 電路的操作頻率 33
第4章電路的實現與模擬 35
4.1 相關電路之簡介設計流程介紹 35
4.2 延遲時間及解析度的考量 36
4.3 負載延遲元件的設計 36
4.4 電路佈局與佈局後模擬圖 39
4.5 晶片量測環境 46
4.6 晶片量測結果及過程 50
4.6.1 第一次量測 50
4.6.2 第二次量測 52
4.6.3 第三次量測 54
4.7 總結和規格比較表 57
第5章結論 59
5.1 結論 59
5.2 未來改進的方向 61
參考文獻 62

參考文獻

[1] Takanori Saeki, Yuji Nakaoka, Mamoru Fujita et al, “A 2.5-ns Clock Access 250-MHz 256-Mb SDRAM with A Synchronous Mirror Delay,” IEEE International Solid-State Circuits Conference Dig. Tech. Paper, pp. 374-375, Feb. 1996.
[2] Takanori Saeki, Yuji Nakaoka, Mamoru Fujita et al, “A 2.5-ns Clock Access, 250-MHz, 256-Mb SDRAM with Synchronous Mirror Delay,” IEEE J. Solid-State Circuits, vol. 31, no 11, pp. 1656-1668, Nov. 1996.
[3] Takanori Saeki, Hideyuki Nakamura, and Junzoh Shimizu “A 10ps Jitter 2 Clock Cycle Lock Time Cmos Digital Clock Generator Based on An Interleaved Synchronous Mirror Delay Scheme,” Symposium on VLSI Circuits, Dig. Tech. Paper, pp. 109-110, Jun. 1997.
[4] Takanori Saeki, Koichiro Minami, Hiroshi Yoshida, and Hisamitsu Suzuki “The direct skew detect synchronous mirror delay (Direct SMD) for ASICs,” Custom Integrated Circuits Conference, pp. 511-514, May 1998.
[5] Takanori Saeki, Koichiro Minami, Hiroshi Yoshida, and Hisamitsu Suzuki “A direct-skew-detect synchronous mirror delay for application-specific integrated circuits,” IEEE J. Solid-State Circuits, vol. 34, no 3, pp. 372-379, Mar. 1999.
[6] Kihyuk Sung and Lee-Sup Kim “A High-resolution Synchronous Mirror Delay Using Successive Approximation Register,” IEEE J. Solid-State Circuits, vol. 39, no 11, pp. 1997-2004, Nov. 2004.
[7] T. Saeki, Y. Nakaoka, M. Fujita, A. Tanaka, K. Nagata, K. Sakakibara, T. Matano, Y. Hoshino, K. Miyano, S. Isa, S. Nakazawa, E. Kakehashi, J.M. Drynan, M. Komuro, T. Fukase, H. Iwasaki, M. Takenaka, J. Sekine, M. Igeta, N. Nakanishi, T. Itani, I. Yoshida, K. Yoshino, S. Hashimoto, T. Yoshii, M. Ichinose, T. Imura, M. Uziie, S. Kikuchi, K. Koyama, Y. Fukuzo and T. Okuda, “A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay,” IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1656-1668, Nov. 1996.
[8] T. Saeli, K. Minami, H. Yoshida and H. Suzuki, “A direct-skew-detect synchronous mirror delay for application-specific integrated circuits,” IEEE J. Solid-State Circuits, vol. 34, no. 3, pp. 372-379 ,Mar 1999.
[9] Chih-Hao Sun and Shen-Iuan Liu “A Mixed-Mode Synchronous Mirror Delay Insensitive To Supply And Load Variations,” Journal Of Analog Integrated Circuits And Signal Processings, vol. 39, pp. 75-80, Apr. 2004.
[10] Hung, Cheng-Liang; Wu, Chen-Lung and Cheng, Kuo-Hsing “Arbitrary Duty Cycle Synchronous Mirror Delay Circuits Design,” IEEE Asian Solid-State Circuit Conference, pp. 283-286, Nov. 2006.
[11] K. Sung and L.-S. Kim, “A high-resolution synchronous mirror delay using successive approximation register,” IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 1997-2004, Nov. 2004.
[12] K.-H. Cheng, C.-L. Hung and C.-L. Wu, “Arbitrary duty cycle synchronous mirror delay circuits design,” in Proc. IEEE Asian Solid-State Circuits Conference, Hangzhou, 2006, pp. 283-286.
[13] Y.-M. Wang and J.-S. Wang, “A low-power half-delay-line fast skew compensation circuit,” IEEE J. Solid-State Circuits, vol. 39, no. 6, pp. 906-918, Jun. 2004.
[14] J.-G. Maneatis, “Low-jitter process-independent DLL and PLL based on self-biased techniques,” IEEE J. Solid-State Circuits, vol. 31, pp. 1723-1732, Nov. 1996.
[15] K.-H. Cheng, C.-W. Su and S.-W. Lu, “Wide-range synchronous mirror delay with arbitrary input duty cycle,” IEE ELECTRONICS LETTERS, vol.44, no. 11, pp. 655-667, May. 2008.
[16] M.-Y. Kim, D. Shin, H. Chae, and C. Kim, “A low-jitter open-loop all-digital clock generator with two-cycle lock-time,” IEEE Trans. On Very Large Scale Integr. Syst, vol. 17, no. 10, pp. 1461-1469, Oct. 2009.
[17] K.-H. Cheng, K.-W. Hong, C.-H. Chen, and J.-C. Liu, “A high precision fast locking arbitrary duty cycle clock synchronization circuit,” IEEE Trans. On Very Large Scale Integr. Syst, vol.09, no. 7, pp. 1218-1228, 2011.
[18] J. Yuan and C. Svensson, “High-speed CMOS circuit technique,” IEEE J. Solid-State Circuits, vol. 24, no. 1, pp. 62-70, Feb. 1989.
[19] P. Larsson and C. Svensson, “Impact of clock slope on true single phase clocked (TSPC) CMOS circuits,” IEEE J. Solid-State Circuits, vol. 29, no. 9, pp. 723-726, Jun. 1994.
[20] HSPICE User Guide: Analyzing electrical yields, Ver. C-2009.03, Mar., 2009.
[21] Y. J. Yoon, H. I. Kwon, J. D. Lee, B. G. Park, N. S. Kim, U R Cho, and H. G. Byun, “Synchronous Mirror Delay for Multiphase Locking,” IEEE J. Solid-State Circuits, vol. 39, no. 1, Jan. 2004.

指導教授

鄭國興(Kuo-Hsing Cheng)

審核日期

2012-7-24

推文