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姓名	許世玄(Shyh-Shyuan Sheu)  查詢紙本館藏	畢業系所	電機工程學系
論文名稱	新興非揮發性記憶體之變異感知電路設計技術 (Variation-Aware Circuit Design Techniques for Emerging Non-volatile Memory)
相關論文	★ 一種應用於觸控液晶顯示器的新型嵌入式開關 ★ 多重相位之延遲鎖定迴路倍頻器設計與分析 ★ 2.5Gbps串列收發器設計 ★ 具低抖動與可適應式頻寬之自我偏壓鎖相迴路設計 ★ 應用於串列傳輸之2.5GB/s CMOS 超取樣資料回復電路 ★ 全數位任意責任週期之同步映射延遲電路 ★ 全數位式互補金屬氧化半導自我取樣延遲線電路用於時脈抖動量測 ★ 500MHz,30個相位輸出之鎖相迴路應用於三倍超取樣時脈回復系統 ★ 設計於90奈米製程輸出頻率為100MHz-1GHz之具可適應性頻寬鎖相迴路 ★ 高解析度可變動責任週期之同步複製延遲電路 ★ 奈米CMOS晶片內序列傳輸之接收器 ★ 奈米CMOS晶片內序列傳輸之送器 ★ 基於鎖相迴路之多重相位脈波產生器 ★ 低能量時脈儲存元件之分析、設計與量測 ★ 具有預先增強器之Gbps串列連結傳送器及全數位超取樣資料回復器 ★ 應用於10Gbps晶片系統傳輸鏈之低抖動自我校準鎖相迴路設計
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摘要(中)	消費性電子產品的發展以多功能、高效能、長待機時間及輕薄短小為主要趨勢，其產品中所需之記憶體未來亦朝向大容量、高讀寫速度、低功率消耗及高使用壽命邁進。長期以來，記憶體從SRAM、DRAM等揮發性記憶體為主的技術、慢慢朝向以Flash、PCM、MRAM、FeRAM及ReRAM等非揮性記憶體來取代揮發性記憶體或同時共存之技術。非揮發性記憶體具有無電力狀態時，資料仍可保存之特性，因而讓消費性產品具有零待機功率消耗與快速開機等優勢。目前非揮發性記憶體主流以Flash記憶體為主流。然而Flash資料讀寫的時間長(約us~ms)，限制產品操作速度; 而其讀寫次數(endurance)只有約105次，限制產品之使用壽命。面對Flash所將面臨的技術瓶頸，許多國內外大廠與研究機構均紛紛投入相變化記憶體(PCM)、磁性記憶體(MRAM)、鐵電記憶體(FeRAM)及電阻式記憶體(ReRAM)等下世代記憶體的開發，期望找出同時具有高讀寫速度、高讀寫次數，低電流寫入，低功率消耗之非揮發性記憶體以應用於未來的消費性產品需求。而本論文即是探討下世代記憶體中的PCM及RRAM，並分別討論其特性、面臨到的問題瓶頸、改善方法與Macro電路設計。 首先，本論文將提出目前記憶體的趨勢與需求，其次將針對PCM之特性予以分析討論，由於PCM主要特性是以內部晶格型態來儲存記憶體狀態。當晶格為結晶態(crystalline)時，為低阻態; 反之，當晶格為非晶態(amorphous)時，為高阻態。由於晶格型態是使用熱能來改變，因此PCM將使用電壓或電流流經元件以產生改變晶格型態所需之熱能。也因此將有電壓寫入與電流寫入二種方法與寫入電路。然而在記憶體Macro中，較長位元線(large number cells per bit-line)容易因為RC delay關係，造成寫入能量不足而導致元件無法轉態，降低記憶體可靠度。本篇文章將採用電流式寫入電路，並提出一自動偵測並補償較長位元線(large number cells per bit-line)所造成寫入能量不足之方法與電路，以提升其記憶體可靠度。 接著本論文將提出速度及耐熱度都比PCM要佳的ReRAM。ReRAM是以氧空缺造成filament形成或斷裂，來決定低阻態或高阻態。但因filament本身的鍵結，會有不同的變異，導致寫入之成功率下降，本論文提出寫入驗證電路，在寫入時予以進行驗證是否寫入成功，以提高記憶體可靠度。 論文最後將討論PCM 與ReRAM各自的優勢與缺點，並將提出未來ReRAM繼續發展之工作與未來之挑戰，以期ReRAM能應用於未來輕、薄、快速、待機時間長之新世代產品。
摘要(英)	The development goals of consumer electronics products are multi-function, high performance, long standby time, small and thin. The memories of these products need high density, high read/write speed, low power consumption and long life time. The volatile memories including SRAM and DRAM have been used for long time. Nowadays, the volatile memory was integrated with non-volatile memory in many applications. The volatile memory in some products were even replaced by non-volatile memory to achieve the advantage of low power consumption. The non-volatile memory has many advantages, such as data storage without power supplication, zero standby power, and instant reboot. At present, the main stream non-volatile memory is Flash memory due to its low cost and power consumption. However, the Flash technology still have some issues to limit it development, such as slow write speed (us~ms), poor endurance (105) and higher write voltage ( > 5 Volt). For the request of future consumer products, many famous companies start to research several emerging non-volatile memories, such as phase change memory (PCM), magnetic memory (MRAM), Ferro-electric memory (FERAM) and resistive memory (ReRAM). This thesis focuses on two promising memories including PCM and RRAM. At first, the introduction of memory technology was addressed. The second is the PCM characteristic. The resistance of PCM is dependent on the crystal structure of the phase change material. When phase change material of PCM device is crystalline, the device is low resistance state (LRS). When phase change material of PCM device is amorphous state, this device is high resistance state (HRS). Because the resistance change of the PCM device is by using joule heat, the device needs to be applied current or voltage to change its resistance state. Hence, two types of write circuit are implemented in peripheral circuit. One is current write circuit and another is voltage write. However, the large number of cells per bit-line has write fail due to the RC delay effect. The RC delay effect will cause the insufficient energy and fail the write operation. In this paper, a path tracking write scheme and circuit has been proposed. With this circuit, the large number cells per bit-line will compensate the energy by the path tracking write circuit to improve the reliability of PCM operation Next, this thesis proposes the ReRAM technology. The ReRAM device has many outstanding characteristics, including fast switching speed and high temperature reliability. These performances of RRAM are better than those of PCM. The resistance of ReRAM is decided by the connection or rupture of conductive filaments which is composed of oxygen vacancies. However, the over-RESET, which weakens the filament structure, leads to write failure. This paper proposed the write-verify circuit to prevent the over-RESET and improve the reliability. Finally, the comparison between PCM and ReRAM are discussed. The challenge and future work are also proposed in the last chapter. For the ultra-slim, high performance, and high life time product request, the emerging non-volatile memory will combination the 3DIC technology to achieve these request of future product.
關鍵字(中)	★ 讀取驅動電路 ★ 寫入驅動電路 ★ 電阻式隨機存取記憶體 ★ 相變化記憶體	關鍵字(英)	★ read driver ★ write driver ★ resistive random access memory ★ phase change memory
論文目次	Contents 摘要 i Abstract iii 誌謝 vi Contents viii Figure Captions x Table Captions xiii Chapter 1 Introduction 1 1.1 Motivation 1 1.2 PRAM and RRAM Concerns 3 1.3 Thesis Organization 4 Chapter 2 Introduction and Design Challenges of PCM 6 2.1 Introduction of PCM 6 2.2 Model of Double-Confined PCM 10 2.3 Design Challenge of PCM 13 2.3.1 VOLTAGE WRITE DRIVER VS. CURRENT WRITE DRIVER 13 2.3.2 INSUFFICIENT ENERGY AT LARGE BITLINE LOAD 15 2.3.3 INSUFFICIENT ENERGY AT LARGE BITLINE LOAD 17 Chapter 3 4Mb Macro Design with Path-Tracking Write Scheme for Bitline-Load Variation Tolerance 18 3.1 Architecture of 4Mb Macro with Path-Tracking Write Circuit 18 3.1.1 PATH-TRACKING WRITE SCHEME AND CIRCUIT 19 3.1.2 READ CIRCUIT 24 3.2 Experimental Results 27 3.2.1 CONCEPT 27 3.2.2 MEASUREMENT RESULTS OF THE PCM MACRO 27 Chapter 4 Introduction and Design Challenges of ReRAM (RRAM) 32 4.1 Introduction of RRAM 32 4.1.1 RRAM DEVICE CHARACTERISTICS 32 4.1.2 DEVICE RELIABILITY 36 4.1.3 MULTI-LEVEL CELL CHARACTERISTIC 38 4.2 Design Challenges of RRAM 41 4.2.1 OVER-RESET PROBLEM 41 4.2.2 SENSING MARGIN OF MULTI-LEVEL OPERATION 43 Chapter 5 RRAM Macro Design with Variation-Aware Circuit 44 5.1 Architecture of 1Kb RRAM Macro 44 5.1.1 WRITE CIRCUIT OF RRAM 45 5.1.2 READ CIRCUIT OF RRAM 48 5.1.3 MULTI-LEVEL OPERATION 50 5.1.4 WRITE-VERIFY OF MULTI-LEVEL OPERATION 53 5.1.5 WRITE RESISTANCE TRACKING CIRCUIT 56 5.2 Experimental Result 63 5.2.1 EXPERIENTIAL RESULTS OF THE 1-KB MACRO 63 5.2.2 EXPERIMENTAL RESULTS OF THE 4-MB MACRO 70 Chapter 6 Conclusions and Future Works 75 6.1 Conclusions 75 6.2 Future Works 78 References 80 Publication List 86 Patents 90 Figure Captions Fig. 1.1.1. MCU block diagram 1 Fig. 1.1.2. Comparison characteristic of emerging memory. . 2 Fig. 2.1.1. : Cross-sectional TEM image of double-confined cells fabricated on top of a CMOS, and schematic of a double-confined cell. 6 Fig. 2.1.2 : Cross-section of double-confined cells. 7 Fig. 2.1.3 R-I curve of a double-confined cell. 8 Fig. 2.1.4 I-V behaviors of a double-confined cell. 8 Fig. 2.1.5 Current amplitude and pulse-width relationship of SET and RESET operations. 9 Fig. 2.2.1. HSPICE model of PCM device. 10 Fig. 2.2.2. Simulation waveform of HSPICE model. 12 Fig. 2.3.1 Induced write current vs. BL loads. 14 Fig. 2.3.2. Current hold time vs. BL loads in CWD. 14 Fig. 2.3.3. Programming voltage versus resistance with different RESET current hold times (pulse widths). 16 Fig. 3.1.1 The architecture of 4Mb PCM Macro 19 Fig. 3.1.2 Path-tracking circuit with different write paths 21 Fig. 3.1.3 Simulation results of PTC-detected voltages (VA1, VA2, and VA3) with different cells per BL 22 Fig. 3.1.4. Through current of PCM cell of the PTW architecture. 23 Fig. 3.1.5. Simulation result of energy with different cells per BL. 24 Fig. 3.1.6. Read circuit of 4Mb PCM macro 25 Fig. 3.1.7. Simulation results of read circuit 26 Fig. 3.2.1 Die micrograph of the PCM 1-Kb macro. 28 Fig. 3.2.2 Die micrograph of the PCM 4-Mb macro 28 Fig. 3.2.3. Resistance distribution of PCM 1-Kb macro 29 Fig. 3.2.4. Resistance distribution of 4-Mb PCM macro 30 Fig. 3.2.5 Read access time of 4-Mb PCM test chip. 30 Fig. 4.1.1. Concept of RRAM cell operation 33 Fig. 4.1.2. The RRAM cell structure 33 Fig. 4.1.3. The I-V curve of RRAM cell 34 Fig. 4.1.4 The operation method of RRAM 35 Fig. 4.1.5 Cycling test of RRAM cell 37 Fig. 4.1.6 Cycling test of RRAM with 40-ns pulse width 37 Fig. 4.1.7 Cycling test of RRAM at 200oC 38 Fig. 4.1.8 I-V curve of multi-level RRAM cell by controlling SET current. 39 Fig. 4.1.9 Resistance of a multi-level RRAM cell in a 150-cycle endurance test 39 Fig. 4.2.1. Cycle test of healthy RRAM device 42 Fig. 4.2.2. Cycle test of HRS failure in the RRAM device 42 Fig. 4.2.3. The level-to-level sensing margin of MLC operation 43 Fig. 5.1.1 Macro structure and read/write circuits. 45 Fig. 5.1.2. Write circuit of 1Kb chip. 46 Fig. 5.1.3. Simulation waveform of SET operation. 47 Fig. 5.1.4. Simulation waveform of RESET operation. 47 Fig. 5.1.5. The read circuit of RRAM macro 48 Fig. 5.1.6. Simulation waveform of read 0 (RRAM cell at LRS). 49 Fig. 5.1.7. Simulation waveform of read 1 (RRAM cell at HRS). 49 Fig. 5.1.8 Multi-level write circuit 50 Fig. 5.1.9 Multi-level read output circuit 51 Fig. 5.1.10 Multi-level read output circuit 52 Fig. 5.1.11 Write-verify procedure of MLC operation 53 Fig. 5.1.12 Schematic of MLC write-verify circuit 54 Fig. 5.1.13 Simulation waveform of MLC write-verify operation (write successful) 55 Fig. 5.1.14 Simulation waveform of MLC write-verify operation (write fail) 56 Fig. 5.1.15. The conventional write-verify and proposed write resistance tracking method 58 Fig. 5.1.16 The write path of 1-kb chip architecture with WRTC block diagram 59 Fig. 5.1.17 The schematic of WRTC 60 Fig. 5.1.18 The timing diagram of internal control signals 61 Fig. 5.1.19 The simulation waveform of WRTC 62 Fig. 5.2.1 Photograph of 1-Kb chip RRAM 64 Fig. 5.2.2 Resistance distribution of SLC-mode at 100 cycles. 64 Fig. 5.2.3 Resistance distribution of the MLC-mode at 100 cycles 65 Fig. 5.2.4 Measured waveform of 1Kb RRAM chip at SLC-mode 66 Fig. 5.2.5 Measured waveform of 1Kb RRAM chip at MLC-mode 67 Fig. 5.2.6 the weibull plot of HRS in 1-kb chip of HfOx RRAM before/after verification. 68 Fig. 5.2.7 Photograph of 4-Mb macro. 70 Fig. 5.2.8 The read/write measurement waveform of 4Mb Macro. 71 Fig. 5.2.9 Resistance distribution of four levels: (a) without write-verify scheme and (b) with write-verify scheme. 72 Table Captions Table 1.1 NVM comparison 3 Table 2.1 SET and RESET condition formulae of the PCM cell 11 Table 2.2 SET and RESET conditions of PCM model 12 Table 3.1 Summary of PCM 4Mb macro performance 31 Table 4.1 Operation conditions of proposed RRAM device 36 Table 4.2 Operation conditions of MLC RRAM 40 Table 5.1 Summary of 1Kb RRAM macro performance 69 Table 5.2 Summary of 4Mb RRAM macro performance 72 Table 5.3 Comparison performance of RRAM macros 73 Table 5.4 Comparison performance of emerging memory macros 74
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指導教授	張孟凡、鄭國興 (Meng-Fan Chang、Kuo-Hsing Cheng)	審核日期	2012-7-24
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