考慮佈局樣板內寄生元件效應的類比電路設計自動化方法

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姓名

丁宜菁(Yi-ching Ding) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

考慮佈局樣板內寄生元件效應的類比電路設計自動化方法
(Template-Based Parasitic-Aware Synthesis Approach for Analog Circuits)

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摘要(中)

隨著製程的演進，晶片的尺寸也逐年下降，製程變異以及電路佈局(Layout)所產生的寄生效應對於晶片的影響也越來越顯著，然而在傳統類比電路設計自動化流程中並沒有很仔細地考慮寄生效應的影響，因為這會耗費相當多的模擬時間。
本篇論文提出一套考慮電路佈局所產生之寄生效應的類比積體電路自動化設計流程。使用佈局樣板預估出寄生電阻電容值後，將預估之數值加入電壓驅動設計方法，並使用非線性規畫去找出最佳解。加入寄生效應之自動化設計流程可以在佈局前預估佈局後之電路效能，進一步降低佈局前及佈局後電路效能的差異，並且可以避免佈局後電路效能不符合訂定規格又須重新設計的情況發生，大大降低設計時間。跟之前有考慮寄生效應的相關研究相比，我們的研究可以大幅降低所需的計算時間，並且可避免過分設計電路。整套流程以MATLAB實現，而在非線性規劃(nonlinear programming)的部分用MATLAB的 Optimization tool box來找尋最佳解，而在自動產生電路佈局上則是以C/C++及Tcl/Tk 程式語言實現，自動化佈局的過程能在Laker環境下執行。從實驗數據的觀察可知，本論文所提出的方法可以在非常短的時間內達到設計出符合使用者所給定規格之電路，並在佈局後電路效能皆有達到訂定規格的標準。

摘要(英)

In deep submicron process, process variation and parasitic effects make a great impact on chip performance. However, the parasitic effects are often not well considered in traditional circuit sizing flow due to the long simulation time with complex parasitic devices. This thesis proposes an automatic design flow for analog circuits, which considers the parasitic effects during synthesis. Considering the possible parasitic resistance and capacitance in the given layout template, a bias-driven optimization approach based on nonlinear programming is proposed to generate an optimal design. The parasitic-aware sizing flow successfully reduces the performance shift after layout and prevents the possible redesign loops. Compared with the traditional simulation-based approaches, the proposed equation-based approach can achieve the required specifications with less computation and less overdesign. The proposed sizing algorithm has been implemented with the optimization tool box in MATLAB, incorporating with an automatic layout generation tool implemented with C/C++, Tcl/Tk and Laker. As demonstrated on several cases, the proposed approach is indeed an effective and efficient solution to achieve the required specification after layout.

關鍵字(中)

★ 樣板
★ 寄生效應
★ 類比設計自動化

關鍵字(英)

★ analog synthesis
★ parasitic-aware
★ Template-based

論文目次

摘要 i
Abstract ii
致謝 iii
目錄 iv
圖目錄 vii
表目錄 x
第一章、緒論 1
1-1 研究動機 1
1-2 相關研究 5
1-3 問題定義 10
1-4 論文結構 11
第二章、背景知識 12
2.1 類比電路佈局議題 12
2.1.1 匹配(Symmetry) 12
2.1.2 對稱(symmetry) 13
2.1.3 相近(proximity) 14
2.1.4 保護環 (guard ring) 14
2.2 佈局產生的寄生效應之影響 16
2.2.1 電晶體內部寄生效應 17
2.2.2 導線上寄生效應 17
2.2.3 寄生效應造成的延遲現象 (RC delay) 19
2.2.4 電流及電阻所造成的電壓差 (IR drop) 23
2.2.5 未考慮寄生效應之電路設計實例 25
2.3 兩級式運算放大器基本架構 26
2.3.1 補償電路 27
2.3.2 電晶體操作偏壓限制 28
2.3.3 佈局樣板 30
2.4 電壓驅動設計方法 31
2.4.1 gm/ID的特性 33
2.4.2 非線性規劃 35
第三章、加入佈局考量之自動化設計 36
3.1 gm/ID 和 gds/ID之表格 (Look-up table) 37
3.2 萃取寄生效應的數值 39
3.2.1 電晶體內部的寄生效應 39
3.2.2 導線上的寄生效應 42
3.3 考慮佈局寄生效應之限制條件與目標函數 44
3.4 考慮寄生效應之自動化電路設計步驟 48
3.5 考慮寄生效應之類比電路自動化設計範例 50
3.5.1 兩級式運算放大器主體電路 50
3.5.2 設計補償電路 55
第四章、實驗結果與分析 57
4.1 實驗環境及佈局工具 57
4.2 實驗結果 59
4.2.1 準確度驗證 59
4.2.2 電路實驗結果 60
第五章、結論 63
參考文獻 64

參考文獻

[1] R.A Rutenbar., “Design Automation for Analog: The Next Generation of Tool Challenges ”
[2] A. Agatwal, H. Sampath, V. Yelamanchili and R. Vemuri, “Fast and Accurate Parasitic Capacitance Models for Layout-Aware Synthesis of Analog Circuit” 41st Design Automation Conference, 2004.
[3] L. Zhang, N. Jangkrajarng, S. Bhattacharya and C.-J. Richard Shi ,“Parasitic-Aware Optimization and Retargeting ofAnalog Layouts: A Symbolic-Template Approach” IEEE transactions on Computer-Aided Design of Integrated Circuits and Systems , vol.27 , no.5 , pp.791-802 , MAY. 2008.
[4] N. Jungkrujarng, S. Bhattacharyu, R. Hurtono and C. -J. Richard Shi, “Automatic Analog Layout Retargeting for New Processes and Device Sizes” International Symposium on Circuit and Systems (ISCAS) , 2003
[5] H. Habal and H. Graeb, “Constraint-Based Layout-Driven Sizing of Analog Circuits” IEEE transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.30, no.8 , pp.1089-1102 , AUG. 2011
[6] N. Jangkrajarng, L. Zhang, S. Bhattacharya, N. Kohagen, and C.-J. Richard Shi “Template-Based Parasitic-Aware Optimization andRetargeting of Analog and RF Integrated Circuit Layouts,” International Conderence on Computer-Aided Design (ICCAD), 2006.
[7] S. Bhattacharya, N. Jangkrajarng and C-J. Richard Shi, ” Template-Driven Parasitic-Aware Optimization of Analog Integrated Circuit Layouts” Design Automation Conference, 2005.
[8] A. Pradhan and R. Vemuri, “A Layout-aware Analog Synthesis Procedure Inclusive of Dynamic Module Geometry Selection” 18th ACM Great Lakes symposium on VLSI
[9] H. Yang, R. Vemuri, “Efficient Symbolic Sensitivity based Parasitic-Inclusive Optimization in Layout Aware Analog Circuit Synthesis”, 20th International Conference on Embedded Systems, 2007.
[10] A. Pradhan and R. Vemuri, “On the Use of Hash Tables for Efﬁcient Analog Circuit Synthesis”, 21st Internation Conference VLSI design (VLSID) ,2008
[11] M. Ranjan, W. Verhaegen, A. Agarwal , H. Sampath , R. Vemuri and G. Gielen, “Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models” Design , Automation and Test in Europe Conference and Exhibition, 2004.
[12] M. Dessouky , M.-M. Lou‥erat and Jacky Porte “Layout-Oriented Synthesis of High Performance Analog Circuits”, Design , Automation and Test in Europe Conference and Exhibition, 2000.
[13] Z. Li and L. Zhang, “A Performance-Constrained Template-Based Layout Retargeting Algorithm for Analog Integrated Circuits” 15th Asia and South Pacific , Design Automation Conference (ASP-DAC), 2010
[14] A. Agarwal and R. Vemuri, “Layout-Aware RF Circuit Synthesis Driven by Worst Case Parasitic Corners”, IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD), 2005
[15] 黃弘一,”Ch03-Analog Layout Consideration,”混合訊號積體電路佈局與分析課程講義，Jan.2001.
[16] M. Eick, M. Strasser, H. Graeb, U. Schlichtmann,”Automatic Generation of Hierarchical Placement Rules for Analog Integrated Circuits,” ISPD’10, March 14–17, 2010
[17] 林柏宏, “階層式類比電路之擺置,” 國立台灣大學電機資訊學院電子工程學博士論文, June. 2009.
[18] L. E. Han,”CMOS Transistor Layout KungFu,”2005
[19] S.Bhattacharya, N.Jangkrajarng, C.J.R. Shi,”Multilevel Symmetry-Constraint Generation for Retargeting Large Analog Layouts,” IEEE transactions on computer-aided design of integrated circuits and systems, vol.25 , no.6, june 2006
[20] B. Razavi, “Design of analog CMOS integrated circuits”, McGraw-Hill Higher Education, 2001
[21] Electronics Tutorial about the RC Time Constan : RC charging circuit . Available at: http://www.electronics-tutorials.ws/rc/rc_1.html
[22] 鄭國興, “Digital Integrated Circuits Design” 數位積體電路設計上課講義，Sep.2009
[23] 詹立宇, “可改善幾何演算法之精準度的電壓趨動運算放大器自動化設計方法,” 國立中央大學電機工程研究所碩士論文, July 2011
[24] M. S. Bazarar, H. D. Sherali, and C. M. Shetty, “Nonlinear Programming,” Wiley, 1993, 2nd ed.
[25] F. Silveira, D. Flandre, P.G.A. Jespers, ” A gm/ID based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA,” IEEE J. Solid-State, vol. 31, no. 9, 1996, pp. 1314-1319.
[26] W. Gao, R. Hornsey, “A power optimization method for CMOS op-amps using sub-space based geometric programming,” IEEE Design Automation and Test in Europe, 2010, pp. 508-513.
[27] http://www.mathworks.com/help/toolbox/ident/ref/bandwidth.html
[28] http://www.mathworks.com/help/toolbox/control/ref/margin.html
[29] SpringsoftR LakerR ，取自
http://www.springsoft.com/ch/community/springsoft-foundation。
[30] 許家綾,“具備內建樣板之鎖相迴路佈局自動化軟體 ,” 國立中央大學電機工程研究所碩士論文, July 2011

指導教授

劉建男(Chien-Nan Liu)

審核日期

2012-8-17

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