降低不匹配效應之力導向電容擺置方法

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姓名

謝崇暉(Chung-Hui Hsieh) 查詢紙本館藏

畢業系所

電機工程學系

論文名稱

降低不匹配效應之力導向電容擺置方法
(Force-Directed Capacitor Placement Considering Mismatches)

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摘要(中)

隨著製程的演進，在類比積體電路設計中，實現精確的電容比例是一項很重要的議題，尤其是類比/數位轉換器及切換式電容。在類比積體電路製造過程中，製程變異通常會造成元件的不匹配。不匹配現象主要分成兩類：系統性不匹配和隨機性不匹配。造成系統性不匹配的主要原因是在擺置時，元件呈現不對稱的擺放狀態而產生製程梯度，使整體的元件不匹配，甚至造成良率下降。造成隨機性不匹配的主要原因是在晶片製造過程中，隨機的波動及材料的特性會影響多項物理性質的參數，使得設計的實際功能和預期有落差。在之前的研究有提出將電容平均分散，可以將空間相關係數升高，也可有效的降低隨機性不匹配。
本篇論文提出一個可降低電容比例不匹配的力導向電容擺置演算法。在初始擺置階段，我們使用有效且快速的方式產生對稱且分散的電容擺置，並於力導向演算法中，將空間相關性模型的特性應用於吸引力及排斥力，使電容移動至力平衡的位置且能增加空間相關係數。所有電容處於力平衡狀態後，我們應用最大權重二分匹配演算法於合法化階段，利用電容與格點的距離當作權重，以迅速地找出電容最適當的位置。實驗結果顯示，與使用模擬退火的演算法比較，我們的方法可以在較短的時間內產生出空間相關係數較高的電容擺置，進而降低不匹配效應。

摘要(英)

As the process technology progresses, one of the most important issues in analog designs is to achieve accurate capacitance ratios, such as analog-to-digital converters and switched-capacitor circuits. In the manufacturing process of analog integrated circuits, capacitor mismatch is usually caused by process variation. There are two types of capacitor mismatch: systematic and random mismatches. To reduce systematic mismatch, designers usually adopt a symmetry structure, to average the mismatch effects induced by process gradients. Capacitors should be distributed uniformly as possible to overcome random mismatch, which means they should exhibit the highest degree of dispersion.
In this paper, we present a force-directed capacitor placement algorithm to reduce the capacitor mismatch. In the initial placement stage, we use an effective and fast way to generate a symmetric and distributed placement. In force-directed stage, the spatial correlation model is applied to the attractive and repulsive forces to let ca-pacitors equilibrium. Finally, we utilize maximum-weight bipartite matching algorithm to efficiently legalize capacitors. Experimental results show that, compared with an SA-based placement method, ours placement method uses shorter running time to generate a higher dispersion structure, which is effective to reduce random mismatch.

關鍵字(中)

★ 力導向
★ 電容擺置
★ 不匹配

關鍵字(英)

★ Force-Directed
★ Mismatch
★ Capacitor Placement

論文目次

摘要 i
Abstract ii
致謝 iii
目錄 iv
圖目錄 vii
表目錄 x
第一章、緒論 1
1-1 前言 1
1-2 背景 2
1-3 研究動機 3
1-4 問題定義 4
1-5 論文架構 5
第二章、相關研究 6
2-1 空間相關性模型 (Spatial Correlation Model) 6
2-2 啟發式演算法 (Heuristic Algorithm) 8
2-3 降低不匹配共質心電容擺置 11
第三章、力導向演算法 16
3-1 力導向演算法流程圖 16
3-2 初始擺置 (Initial Placement) 17
3-3 力導向擺置 (Force-Directed Placement) 19
3-3-1 吸引力 (Attractive Force) 19
3-3-2 排斥力 (Repulsive Force) 20
3-3-3 邊界條件 (Boundary Constraint) 23
3-3-4 移動平衡條件 (Equilibrium Constraint) 24
3-4 合法化 (Legalization) 25
3-5 優化 (Refinement) 27
第四章、實驗結果與分析 29
4-1 工作平台與測試檔說明 29
4-2 實驗結果與比較 30
第五章、結論 34
參考文獻 35

參考文獻

[1] Jwu-E Chen, Pei-Wen Luo, and Chin-Long Wey, “Yield Evaluation of Analog Placement with Arbitrary Capacitor Ratio,” Proc. International Symposium on Quality Electronic Design (ISQED), pp. 179-184, 2009.
[2] Jwu-E. Chen, Pei-Wen Luo, and Chin-Long Wey, “Placement Optimization for Yield Improvement of Switched-Capacitor Analog Integrated Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 29, no. 2, pp. 313-318, February, 2010.
[3] Thomas M. J. Fruchterman and Edward M. Reingold, “Graph Drawing by Force-Directed Placement,” Software-Practice and Experience, vol. 21, pp. 1129-1164, November, 1991.
[4] DiaaEldin Khalil, Mohamed Dessouky, Vincent Bourguet, Marie-Minerve Louerat, Andreia Cathelin, and Hani Ragai, “Evaluation of Capacitor Ratios in Automated Accurate Common-Centroid Capacitor Arrays,” Proc. International Symposium on Quality Electronic Design (ISQED), pp. 143-147, 2005.
[5] Scott Kirkpatrick, C. Daniel Gelatt, and Mario P. Vecchi, “Optimization by Simulated Annealing,” Science, vol. 220, no. 4598, pp. 671-680, May, 1983.
[6] Cheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu, Chun-Po Huang, and Soon-Jyh Chang, “Common-Centroid Capacitor Placement Considering Systematic and Random Mismatches in Analog Integrated Circuits,” Proc. Design Automation Conference (DAC), pp. 528-533, 2011.
[7] Pei-Wen Luo, Jwu-E Chen, Chin-Long Wey, Liang-Chia Cheng, Ji-Jan Chen, and Wen-Ching Wu, “Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 27, no. 11, pp. 2097-2101, Novenber, 2008.
[8] Hiroo Masuda, Shin-Ichi Ohkawa, Atsushi Kurokawa, and Masakazu Aoki, “Challenge: Variability Characterization and Modeling for 65- to 90-nm Processes,” Proc. IEEE Custom Integrated Circuits Conference (CICC), pp. 593-599, 2005.
[9] Michael J. McNutt, Sabine LeMarquis, and James L. Dunkley, “Systematic Capacitance Matching Errors and Corrective Layout Procedures,” IEEE Journal of Solid-State Circuits (JSSC), vol. 29, no. 5, pp. 611-616, May, 1994.
[10] DiaaEldin Sayed and Mohamed Dessouky, “Automatic Generation of Common-Centroid Capacitor Arrays with Arbitrary Capacitor Ratio,” Proc. Design, Automation and Test in Europe (DATE), pp. 576-580, 2002.
[11] Jyn-Bang Shyu, Gabor C. Temes, and Francois Krummenacher, “Random Error Effects in Matched MOS Capacitors and Current Sources,” IEEE Journal of Solid-State Circuits (JSSC), vol. 19, no. 6, pp. 948-955, December, 1984.

指導教授

陳泰蓁(Tai-Chen Chen)

審核日期

2012-8-21

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